Microprocessor having a branch predictor using speculative...

Details Microprocessor having a branch predictor using speculative... Microprocessor having a branch predictor using speculative...

2005-03-22

2005-03-22

Eng, David Y. (Department: 2155)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

06871275

ABSTRACT:
A method and apparatus for speculatively providing a branch target address as specified by an impending branch operation. In one embodiment, a branch prediction unit of the present invention is operable to pre-decode and pre-execute branch operations in a pipestage prior to a decoding stage and an execution stage of a pipelined processor. The branch operations of the present invention are performed via multiple instructions separately scheduled and executed, wherein a first instruction of a branch operation specifies a branch target, and a second instruction of a branch operation specifies when a branch of the branch operation is to occur. In an alternative embodiment of the present invention, the branch prediction unit is further operable to pre-fetch instructions from a memory hierarchy into a local instruction memory device in response to the branch prediction unit pre-decoding a first instruction of a branch operation.

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