Microprocessor for controlling busses

Details Microprocessor for controlling busses Microprocessor for controlling busses

1999-10-26

2003-02-04

Dharia, Rupal (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S240000

Reexamination Certificate

active

06516378

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a microprocessor equipped with a plurality of buses and a plurality of bus masters. More particularly this invention relates to a microprocessor equipped with a bus control unit for efficiently controlling the buses when there are access requests from the bus masters. In a microprocessor used for a control device or a portable electronic apparatus in recent years, there has been generally employed a system having a large number of modules connected on the buses for controlling these modules through the buses in order to achieve complex processes and to enhance expandability of the processing. Particularly, on a microprocessor of which high-speed processing is required, a cache memory and a DMA (Direct Memory Access) controller are mounted to increase the use efficiency of the buses.
BACKGROUND OF THE INVENTION
FIG. 1
is a block diagram which shows a schematic configuration of a conventional microprocessor employing a Harvard architecture. Harvard architecture is one of architectures at a register level, which uses buses for data access (data buses) and buses for instruction access (instruction buses) provided independent of each other. Further in Harvard architecture, a memory connected to the data buses, that is, a data memory, is exclusively used for storing data, and a memory connected to the instruction buses, that is, an instruction memory, is exclusively used for storing instructions. Thus, the data memory and the instruction memory are used as spatially separated addresses. By using this Harvard architecture, the microprocessor can protect instructions and can achieve a parallel operation of accesses, thereby to achieve a high-speed processing.
As shown in
FIG. 1
, the conventional microprocessor
100
includes a CPU (Central Processing Unit)
110
for executing instructions according to program codes, a bus control unit
120
for carrying out a bus arbitration by monitoring the state of using a plurality of buses, an instruction memory
131
as a memory for exclusively storing instructions, a data memory
132
as a memory for exclusively storing data. Further, the microprocessor
100
includes a program ROM
141
for storing a start instruction set and a basic instruction set, a program RAM
142
for storing a user program. Further, the microprocessor
100
includes a DMA controller
143
for directly exchanging data, that is, a DMA transfer, between modules connected to the buses without passing through the CPU
110
and various memories. Further, the microprocessor
100
includes an external bus I/F
151
for being connected to external units, to carry out a functional expansion or data input to and output from the external units, an SDRAM I/F
152
for making it possible to expand an SDRAM (Synchronous Dynamic Random Access Memory) as an extended memory. Finally, the microprocessor
100
includes a peripheral bus I/F
153
for executing a function as an interface with incorporated peripheral devices.
Instruction bus IB and a data bus DB are provided between the CPU
110
and the bus control unit
120
. The program ROM
141
, the program RAM
142
, the DMA controller
143
, the external bus I/F
151
, the SDRAM I/F
152
and the peripheral bus I/F
153
are connected to a common bus, that is a Princeton bus, PB monitored by the bus control unit
120
.
A timer
161
, a UART (Universal Asynchronous Receiver Transmitter)
162
for supporting a serial communication, an analog/digital converter (ADC)
163
, and the like are connected to the peripheral bus I/F
153
as incorporated peripheral devices.
The instruction bus IB, the data bus DB and the Princeton bus PB include a data bus for transferring data and an address bus for transferring an address, respectively. Each module (including the CPU
110
) connected to each of these buses is provided with a not illustrated control bus for transferring control signals such as a bus use request signal necessary for communicating with the bus control unit
120
, a read/write signal, an address strobe signal, a data strobe signal, various acknowledge signals, etc.
In the microprocessor
100
employing the Harvard architecture as shown in
FIG. 1
, the instruction memory
131
and the data memory
132
, in particular, are used as cache memories, to improve throughput. The basic operation of the microprocessor
100
will be explained below.
When the microprocessor
100
is started, a start instruction unit stored in the program ROM
141
is read into the CPU
110
through the Princeton bus PB and the instruction bus IB, and a user program stored in the program RAM
142
is executed when necessary.
In this case, prior to making an access to the program ROM
141
and the program RAM
142
, the CPU
110
checks whether a corresponding instruction is stored in the instruction memory
131
or not. When the corresponding instruction is stored (cache hit), the CPU
110
fetches this instruction from the instruction memory
131
and executes this instruction (instruction fetch).
On the other hand, when the corresponding instruction is not stored in the instruction memory
131
, the CPU
110
fetches the instruction from the program ROM
141
or the program RAM
142
which is the original access destination, and executes this instruction. At the same time, the CPU
110
stores the fetched instruction in the instruction memory
131
. With this arrangement, when it becomes necessary again to execute the instruction once executed by the CPU
110
, it is possible to fetch this instruction from the instruction memory
131
.
As explained above, when the cache hit has been obtained, the instruction fetch can be executed in a shorter clock cycle than in the case of accessing the program ROM
141
or the program RAM
142
. Therefore, a system which can perform processing at a high-speed can be achieved.
Further, when data once fetched from the SDRAM I/F
152
or others is stored in the data memory
132
, in a similar manner to the data stored in the instruction memory
131
, it becomes possible to obtain a cache hit from the data memory
132
when it is necessary to make a data access to the SDMA I/F
152
or others. Thus, a system which can perform processing at a high-speed can be achieved
In this microprocessor
100
, not only the CPU
110
but also the DMA controller
143
can become a bus master. Therefore, the CPU
110
needs to obtain a permission for using the instruction bus IB, the data bus DB and the Princeton bus PB from the bus control unit
120
each time when the CPU
110
carries out the above-described instruction fetch or data access.
In other words, in order to make an access to the program ROM
141
or the program RAM
142
, the CPU
110
transmits a bus use request signal representing a request for using the Princeton bus PB to the bus control unit
120
through the control bus.
The bus control unit
120
checks whether the Princeton bus PB is being used by other bus master or not. For example, when the DMA controller
143
is using the Princeton bus PB for carrying out a DMA transfer from the SDRAM I/F
152
to the external bus I/F
151
, the bus control unit
120
transmits a bus use request signal to the DMA controller
143
. Upon receiving this bus use request signal, the DMA controller
143
goes into a hold state immediately after finishing the bus cycle currently under execution, and then transmits a bus abandon signal to the bus control unit
120
.
The bus control unit
120
transmits a WAIT signal to the CPU
110
to make the CPU
110
wait during a period from when the DMA controller
143
receives the bus use request signal till when the DMA controller
143
transmits the bus abandon signal. Upon receiving the bus abandon signal from the DMA controller
143
, the bus control unit
120
transmits a bus obtaining signal representing an obtaining of a bus right to the CPU
110
. When, the CPU
110
obtains the bus right it can make an access to each unit connected to the Princeton bus PB.
Further, when a bus master like the DMA controller
143
other than the CPU

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