Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2002-03-13
2004-11-23
Peikari, B. James (Department: 2186)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S039000, C712S207000, C712S237000
Reexamination Certificate
active
06823406
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a microprocessor executing a program by replacing an order of read and write.
BACKGROUND OF THE INVENTION
A microprocessor, such as an image processing processor, occasionally executes a program by replacing an order of read and write. Such a microprocessor executes instructions by replacing the order of a read instruction and a write instruction that have been issued from a central processing unit (“CPU”) to a main memory or a peripheral system, according an order of a program, in order to improve a processing performance. According to this kind of microprocessor, when the CPU accesses a register, such as a control register in the peripheral system, but the meaning is different depending on the order of the access, it is necessary to guarantee an access order.
In general, the CPU carries out a processing (operation) by accessing a machine instruction or data that is stored in the main memory. However, because an operation speed of the main memory is extremely lower than that of the CPU, it takes a long processing time to read from and to write to the main memory. Therefore, a cache memory that operates at a higher speed than the main memory is provided between the CPU and the main memory. The instruction or data is temporarily stored in the cache memory, to reduce access to the main memory. Based on this arrangement, a processing time required for read and write is reduced.
FIG. 1
is a schematic diagram that shows an outline of a flow of the data when the CPU writes the data into the main memory. A microprocessor
1
has a CPU
2
and a cache system
3
. The CPU
2
outputs a write data and a write address data (hereinafter, an address data will be simply referred to as an address) to the cache system
3
. The write data and the write address are sent to a main memory
6
via a bus control section (“BUSC”)
5
, and are written into the main memory
6
. The solid black arrows in
FIG. 1
show the flow of data when the CPU writes the data into the main memory.
FIG. 2
is a schematic diagram that shows an outline of a flow of data when the CPU
2
reads the data from the main memory
6
. The CPU
2
outputs an address of the data to be read, that is, a read address, to the cache system
3
. The read address is sent to the main memory
6
via the bus control section
5
. The main memory
6
reads the data corresponding to the read address. The read data is sent to the CPU
2
via the bus control section
5
and the cache system
3
. The solid black arrows in
FIG. 2
show the flow of data when the CPU reads the data from the main memory
6
.
FIG. 3
is a schematic diagram that shows another outline of the flow of the data when the CPU
2
writes the data into a peripheral system
7
. The CPU
2
outputs the write data and the write address to the cache system
3
. The write data and the write address are sent to the peripheral system
7
, via the bus control section
5
, and are written into a control register or the like. The solid black arrows in
FIG. 3
show the flow of the data when the CPU
2
writes the data into the peripheral system
7
.
FIG. 4
is a schematic diagram that shows an outline of the flow of the data when the CPU
2
reads the data from the peripheral system
7
. The CPU
2
outputs the read address to the cache system
3
. The read address is sent to the peripheral system
7
via the bus control section
5
. The peripheral system
7
reads the data corresponding to the read address. The read data is sent to the CPU
2
via the bus control section
5
and the cache system
3
. The solid black arrows in
FIG. 4
show the flow of the data when the CPU
2
reads the data from the peripheral system
7
.
FIG. 5
is a block diagram that shows a detailed structure of a cache system of a conventional microprocessor. As shown in
FIG. 5
, the cache system
3
has a tag RAM
31
that stores an identification address of a cache block, and a cache RAM
32
that stores the data.
The cache system
3
has a wait address register (“WAR”)
33
, a read address register (“RAR”)
34
, a cache write buffer address (“CWBA”)
35
, and a store buffer address (“STBA”)
36
, as registers that store addresses. Further, the cache system
3
has a wait data register (“WDR”)
37
, a cache write buffer (“CWB”)
38
, and a store buffer (“STB”)
39
, as registers that store data. Further, the cache system
3
has five selectors
41
,
43
,
44
,
45
, and
46
, and a tag address comparator
42
. Further, the cache system
3
has a cache control section not shown that controls the cache system
3
.
The operation of the microprocessor shown in
FIG. 5
will be explained.
FIG. 6
is a diagram that shows the flow of the address and a read data when a read access has a cache hit in the microprocessor shown in FIG.
5
. In
FIG. 6
, thick lines show along which routes the address and the data flow (the same applies to
FIG. 7
to
FIG. 17
, and
FIG. 20
to FIG.
23
). The CPU
2
supplies a read address to the tag RAM
31
and the cache RAM
32
via the selector
41
. The tag address comparator
42
compares a tag address with the read address. When the tag address and the read address coincide with each other as a result of the comparison (cache hit), the CPU
2
receives the data that has been read from a way of the cache RAM
32
in which the addresses coincide, via the selectors
45
and
46
. Further, a cache hit signal is asserted.
FIG. 7
is a diagram that shows the flow of the address and the read data when the read access has a cache miss in the microprocessor shown in FIG.
5
. The CPU
2
supplies the read address to the tag RAM
31
via the selector
41
. The tag address comparator
42
compares the tag address with the read address. When these do not coincide with each other as a result of the comparison (cache miss), the read address is stored into the read address register
34
. The stored read address is output to the bus control section
5
together with a read request, until when the read address is accepted by the bus control section
5
.
When the bus control section
5
has accepted the read request and the address, and the bus control section
5
has supplied the read data, the read data is sent to the CPU
2
via the selector
46
, and the data is also stored into the cache RAM
32
via the selector
44
. The cache hit signal is negated. More specifically, the read address is also supplied to the cache RAM
32
from the CPU
32
. However, as the cache miss is explained in this case in
FIG. 7
, a thin line is used to show a section from the selector
41
to the cache RAM
32
instead of a thick line that shows an address supply route (the same applies to FIG.
15
).
FIG. 8
is a diagram that shows the flow of the address and the read data when the write access has cache hit in the microprocessor shown in FIG.
5
. The CPU
2
supplies a write address to the tag RAM
31
and the cache RAM
32
via the selector
41
. The tag address comparator
42
compares the tag address with the write address. When the tag address and the write address coincide with each other as a result of the comparison (cache hit), the write address is stored into the cache write buffer address
35
and the store buffer address
36
.
Further, the write data is stored into the cache write buffer
38
and the store buffer
39
via the selector
43
. The write address stored in the store buffer address
36
and the write data stored in the store buffer
39
are supplied to the bus control section
5
together with a write request. On the other hand, the write address stored in the cache write buffer address
35
is supplied to the tag RAM
31
and the cache RAM
32
. The write data stored in the cache write buffer
38
is written into an area corresponding to the write address of the cache RAM
32
. Further, a cache hit signal is asserted.
FIG. 9
is a diagram that shows the flow of the address and the read data when the write access has cache miss in the microprocessor shown in FIG.
5
. The CPU
2
supplies a write address to the tag RAM
31
vi
Utsumi Hiroyuki
Yamazaki Yasuhiro
Yoda Hitoshi
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