Microprocessor device

Details Microprocessor device Microprocessor device

1998-12-28

2002-03-26

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

06363459

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a microprocessor device having an arithmetic logic unit or central processing unit (CPU) in which the instructions, which are stored in a program memory, for controlling the different components of the microprocessor are converted into arithmetic and/or logical combinations, and having a data and/or control line bus for the transmission of data and for access to CPU-internal and/or peripheral-bound special function registers, which are assigned to the central processing unit.
A multiplicity of microprocessors and microcontrollers are known in the prior art, for example those from the so-called 8051 family of Siemens. The control computer 8051, which was originally developed by Intel Corporation and in the meantime has also become available from other companies in similar forms, has developed in recent years to become one of the standards in the world of 8-bit microcontrollers. The heart of such a microprocessor system is the central processing unit (CPU), which is designed as part of a semiconductor chip on which the other parts of the system are also concomitantly integrated. The CPU essentially consists of three components: an instruction decoder, a central processing unit and an associated sequence controller. In the instruction decoder, the instructions which have been read in from the on-chip or off-chip program memory are decoded and the steps necessary for execution are performed. These comprise various measures, for example fetching further data from the memory, or instructing the central processing unit to carry out specific arithmetic or logical combinations, or causing the sequence controller to jump to a different program location, and the like. The instruction decoder passes the instructions on to the different CPU components by means of numerous internal control signals. The instruction decoder decodes a specific instruction set, that is to say the binary machine instructions of the respective CPU. The logical and arithmetic combinations which the instruction decoder requires in order to process a specific instruction are carried out in the central processing unit or the CPU. The central processing unit with a, for example, 8051-compatible CPU essentially knows addition, subtraction, multiplication, division, as well as the logic combinations AND, OR, EXCLUSIVE-OR, ONE'S COMPLEMENT.
The fundamental method of operation and the structure of such a microcontroller 8051 are known and will not be explained here in every detail. For further details on the architecture and programming of the prior art microprocessor system, reference is therefore expressly made to the entire contents of the following manual: Johannis, Rainer, Handbuch zum 80C517 und 80C517A, Architektur und Programmierung [Manual on the 80C517 and 80C517A, Architecture and Programming], Rainer Johannis and Nikolaos Papadopulus, Siemens Aktiengesellschaft, Berlin, Munich, ISDN 3-8009-4128-7.
Only those components of the previously known microcontroller and its RAM memory division which are essential for an understanding of the invention are explained below, with reference to
FIGS. 1 and 4
. In accordance with
FIG. 1
, in the architecture of the microcontroller 8051 (or ECO2000), the internal RAM memory area
1
having an address field of 256 bytes, for example, is subdivided into three sections
2
,
3
,
4
. The first section
2
comprises the “lower” 128 bytes and is both directly and indirectly addressable (
00
H to
7
FH). Also located in this section
2
are the four register banks
5
,
6
,
7
,
8
each having eight registers of 8 bits (
00
H to
1
FH), as well as an area
9
having 16 bit-addressable bytes (
20
H to
2
FH). The second section
3
of the internal RAM memory
1
comprises the “upper” 128 bytes (
80
H to FFH). The upper 128 bytes are only indirectly addressable. Although a third section
4
has the same address range as the second section
3
, it is only directly addressable. It also contains 16 bytes, namely at all addresses divisible by eight, whose bits are likewise bit-addressable. This area
4
constitutes the so-called special function registers (SFR). This means that the registers of the section
4
are not located in a coherent area, but rather are assigned to the corresponding peripheral components of the microprocessor (timer, UART, interrupt module, co-processor, I/O port and the like). The internal special function registers of the CPU (A, B, Dptr, stack pointer and the like) are also located in this area
4
. In this respect,
FIG. 4
shows a diagrammatic illustration of the RAM memory division used to date in 8051 microprocessors. It illustrates the special function registers
12
,
13
,
14
,
15
,
16
,
17
of the the peripheral components of the microprocessor, as well as the CPU-internal special function register
18
, the indirectly addressable RAM area
19
, the indirectly and directly addressable RAM area
20
, as well as the further internal special function registers
21
of the CPU concerning the A register, B register, DPTRH register, DPTRL register, SP register, DPSEL register and the like. The reference numbers
22
and
23
represent the special function registers EETIME and EEVOLT, which are also referred to below as peripheral-independent special function registers, are realized as individual registers and are each connected separately to the data bus
11
and driven via control lines
10
.
Such a configuration serves the purpose of permitting the fastest and most effective access possible by the CPU to the peripheral components of the microprocessor. Particularly in the case of smart cards, the situation arises where the third memory area
4
illustrated in
FIG. 1
is utilized only very scantily, since only very few peripheral components are used, as a rule, in smart card products. This means that, in spite of intrinsically good software support by the 8051 (or ECO2000) instructions which relate to this third memory section
4
-
39
and
49
of a total of 125 and 187 8051 instructions and ECO2000 instructions, respectively, have a direct address as source or destination—the memory area
4
is virtually wasted. At the same time, however, it is precisely instructions with direct addressing that are usually quite fast and do not require too many bytes, particularly in comparison with the alternative use of a so-called external RAM memory (XRAM), to which, as a rule, access can be made only in a very unfavorable manner with an 8051 architecture. This also applies to the instruction set of the ECO2000, which constitutes a further development of the ECO51 (8051) with a supplemented instruction set, in the case of which the connection of the XRAM memory actually acquired great importance. Nevertheless, such instructions still require slightly more bytes, but above all, in addition, more clock pulses than comparable instructions with direct addresses. Since, however, particularly in smart card applications, the area requirement is of the greatest importance, and the internal RAM memory areas
2
and
3
are almost completely utilized for previous used operating systems, this problem can be circumvented in the sense of the solutions used to date only by means of additional direct addresses in the unutilized area
4
or, in the case of a larger requirement, by means of an XRAM memory which is additionally to be provided. In the previous solution there were admittedly experiments with a plurality of individual special function registers
22
,
23
which were placed in this unutilized area
4
but were not employed in a manner corresponding to the purpose of the area, that is to say as special function registers bound to peripheral components, but rather were used as a pure RAM expansion. However, these registers
22
,
23
were realized only in small associated groups (for example EETIME, EEVOLT) or as individual registers, as has been explained with reference to the diagrammatic illustration in accordance with FIG.
4
. In this case, each individual register or eac

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