Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-11-20
1998-11-10
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711214, G06F 930
Patent
active
058357440
ABSTRACT:
A microprocessor is provided which is configured to locate memory and register operands regardless their use as an A operand or B operand in an instruction. Memory operands are conveyed upon a memory operand bus, and register operands are conveyed upon a register operand bus. Decoding of the source and destination status of the operands may be performed in parallel with the operand fetch. Restricting memory operands to a memory operand bus enables reduced bussing between decode units and the operand fetch unit. After fetching operand values from an operand storage, the operand fetch unit reorders the operand values according to the instruction determined by the associated decode unit. The operand values are thereby properly aligned for conveyance to the associated reservation station.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4742453 (1988-05-01), Shibuya
patent: 4807115 (1989-02-01), Torng
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson et al.
patent: 5136697 (1992-08-01), Johnson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5517657 (1996-05-01), Rodgers et al.
patent: 5649225 (1997-07-01), White et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes on Intel P6," BYTE, Jan. 1996, 4 pages.
Johnson William M.
Tran Thang M.
Witt David B.
Advanced Micro Devices , Inc.
Hinder Patrice L.
Kivlin B. Noel
Lall Parshotam S.
Merkel Lawrence J.
LandOfFree
Microprocessor configured to swap operands in order to minimize does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microprocessor configured to swap operands in order to minimize , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor configured to swap operands in order to minimize will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1527033