Microprocessor configured to execute multiple threads including

Details Microprocessor configured to execute multiple threads including Microprocessor configured to execute multiple threads including

1996-05-17

1999-08-31

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

712214, 712228, 712 23, 710266, G06F 930, G06F 938, G06F 946

Patent

active

059448164

ABSTRACT:
A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently. Multiple tasks may be executed concurrently by the microprocessor in addition to executing multiple interrupt service routines concurrently. In still another embodiment, the microprocessor includes a primary context and multiple local context storages coupled to each of its execution units. A given execution unit may execute instructions referencing the primary context or the local context connected thereto.

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