Electrical computers and digital processing systems: processing – Processing control – Logic operation instruction processing
Reexamination Certificate
2000-05-03
2001-11-13
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Logic operation instruction processing
C712S213000, C712S224000, C712S210000, C712S221000, C708S508000, C708S490000
Reexamination Certificate
active
06317825
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to microprocessors and more particularly to the performance, in a microprocessor, of an operation to concatenate at least one bit of a first binary word with bits of a second binary word.
The concatenation of bits is an operation frequently used in industrial data processing. In particular, the authentication codes sent out by microprocessor cards such as bankcards are generated by encryption algorithms requiring numerous bit concatenation operations. Now, the standard microprocessors have the drawback of using several clock cycles and several program code bytes (i.e. 8-bit words) to carry out this operation.
For example, with a 6805 type microprocessor, the bit concatenation is done by means of “BRSET” and “BCLR” instructions and requires first of all the one-setting of the bits of a memory zone designed to contain the result of the operation. Then, the value of a first bit to be concatenated is tested and the first bit of the memory zone is set at 0 if the bit to be concatenated is equal to 0. Then, the value of the second bit to be concatenated is tested and the second bit of the memory zone is set at 0 if the second bit to be concatenated is equal to 0, etc. The concatenation of each bit in the memory zone requires five program code bytes (including instructions and addressing of the memory) and the execution time is about ten machine cycles.
In an 8051-type microprocessor, the bit to be concatenated is first of all loaded into a flag, for example the CRY or carry flag. Then, the bit is inserted into the working registers of the microprocessor by shifting the register rightward by means of the instruction “ROR” or by direct insertion by means of the instruction “MOV”. Finally, the contents of the working register are loaded into memory. These operations also consume several bytes of code and take several machine cycles.
Ultimately, the prior art microprocessors are slow to execute a program that contains a large number of concatenation operations and, for each concatenation program, they require the writing of several program codes.
There also exist known sophisticated pipeline type microprocessors, namely microprocessors with overlapping of instructions. The advantage of these microprocessors is that they work at high speed. However, these microprocessors have a degree of complexity, space requirement and cost price that makes them unsuitable for integration into chip cards.
In particular, contactless chip cards powered by electromagnetic induction possess low resources in electrical energy and have to be fitted out with a microprocessor that consumes little current while being fast and capable of processing a transaction in a very short period of time of about some microseconds.
There is also the article by Wai Lung Loh, “BEE: a special-purpose machine for hardware description languages”, in the journal
Microprocessors and Microsystems
, Vol. 19, No. 5, June 1995, that describes a hardware circuit emulator programmed by means of a specific VHDL (hardware description language). This article proposes to facilitate the simulation of operations to manipulate bit strings by making a hardware circuit called a BEE (bitstring emulator engine) taking charge of the execution of such operations. However, the BEE circuit is complex and is ill suited to incorporation into a microprocessor designed for chip cards.
Finally, the U.S. Pat. No. 4,023,023 describes a hardware circuit used to make several operations for shifting and concatenating bits from two binary words given at input.
SUMMARY OF THE INVENTION
A general goal of the present invention is to provide for a microprocessor that incorporates a bit concatenation hardware circuit and, at the same time, is easy to design and compact, consumes little power and offers high speed of processing of the instructions of the program, especially a concatenation instruction.
This goal is achieved by providing for a pipeline microprocessor comprising means to decode an instruction for the concatenation of at least one bit of a first binary word with at least one bit of a second binary word; a bank of registers; means to process the concatenation instructions; the microprocessor comprising a first pipeline stage comprising means for decoding the concatenation instruction; a second pipeline stage contiguous to the first stage, comprising a first sector comprising concatenation means in which the bank of registers is laid out in read mode and a second sector in which the bank of registers is laid out in write mode, the first sector being active at each clock half-cycle of the microprocessor and the second sector being active at each following clock half-cycle, the means for processing the concatenation instruction being laid out to read the first and second binary words in a bank of registers and execute the concatenation instruction during a first clock half-cycle and record the result of the concatenation in the bank of registers during the following clock half-cycle.
Advantageously, the concatenation means comprise means for the parallel presentation, on the data path of the microprocessor, of the two binary words read in the back of registers, means for the selection of at least one bit to be concatenated of the first binary word and means to shift bits from the first binary word on the data path and insert at least the selected bit of the first binary word in the second binary word.
Advantageously, the means for shifting bits comprise a hardware wire-switching circuit organized so that, upon the reception of a shift signal, it shifts the rank of the wires of the data path and connects the output of the selection means of the bit to be concatenated to at least one wire of the data path.
According to one embodiment, the means for the selection of at least one bit comprise a multiplexer circuit arranged in the data path to receive the first binary word at input.
According to one embodiment, the second binary word is read in the bank of registers at the concatenation result recording address.
According to one embodiment, the microprocessor comprises means for decoding a compact concatenation instruction comprising a compact address for recording the result of the concatenation.
According to one embodiment, the microprocessor comprises means for decoding a concatenation instruction, the code of which comprises a predetermined compact address for recording the result of the concatenation.
According to one embodiment, the means for decoding the concatenation instruction are laid out to generate a fixed and predetermined address for recording the result of the concatenation.
REFERENCES:
patent: 4023023 (1977-05-01), Bourrez et al.
patent: 4785393 (1988-11-01), Chu et al.
patent: 5144573 (1992-09-01), Greiner
patent: 0 438 126 A2 (1991-07-01), None
patent: 0 664 508 A2 (1995-07-01), None
patent: WO99/23550 (1999-05-01), None
Norman P. Jouppi, “The Nonuniform Distribution of Instruction-Level And Machine Parallelism And Its Effect On Performance”IEEE Transactions On Computersvol. 38 No. 12 pp. 1645-1658, (Dec. 1, 1989).
Wai Lung Loh, “BEE: A Special-Purpose Machine For Hardware Description Languages”Microprocessors And Microsystems, vol. 19, No. 5, pp. 269-276, (Jun. 1, 1995).
Akin Gump Strauss Hauer & Feld L.L.P.
Inside Technologies
Pan Daniel H.
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