Microprocessor circuits, systems, and methods using a combined w

Details Microprocessor circuits, systems, and methods using a combined w Microprocessor circuits, systems, and methods using a combined w

1997-08-28

2000-03-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711133, 711140, 711142, 711143, 711144, 711145, G06F 1208

Patent

active

060386452

ABSTRACT:
A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and operable to evict information. The microprocessor further includes a combined storage queue (16) coupled to the central processor unit core and to the cache circuit. The combined storage queue includes a set of logical storage blocks (22c) which is operable to store both information written by the central processor unit core and information evicted by the cache circuit. Other circuits, systems, and methods are also disclosed and claimed.

REFERENCES:
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patent: 5526508 (1996-06-01), Park et al.
patent: 5526510 (1996-06-01), Akkary et al.
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5642494 (1997-06-01), Wang et al.
patent: 5659709 (1997-08-01), Quach
patent: 5684977 (1997-11-01), Van Loo et al.
patent: 5809524 (1998-09-01), Singh et al.

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