Microprocessor circuits, systems, and methods implementing a loo

Details Microprocessor circuits, systems, and methods implementing a loo Microprocessor circuits, systems, and methods implementing a loo

1997-12-29

1999-09-14

Vu, Viet D.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395383, 711204, G06F 938

Patent

active

059535121

ABSTRACT:
A load target circuit (56) with a plurality of entries (56.sub.1). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.

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Stride Directed Prefetching in Scalar Processors, John W. C. Fu, et al. Intel Corp., 1900 Praire City Rd. Folsom, CA 95630.

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