Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1997-06-09
2004-01-13
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000
Reexamination Certificate
active
06678790
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of computer memories. More particularly, this invention relates to a memory that can be reconfigurable to function as a cache or as main memory.
2. Art Background
Prior computer systems typically include a central processing unit (CPU) along with a main memory. The main memory typically provides general purpose storage of instructions and data for the CPU.
In addition, prior computer systems may include a cache memory. Typically, a cache memory is a fast memory which is closely coupled with the CPU. Such a cache memory usually holds a subset of the instructions and/or data contained in the main memory. A cache memory typically improves the performance of the computer system by providing the CPU with fast access to instructions and/or data.
The CPU in prior computer systems is commonly implemented on a single integrated circuit chip which may be referred to as a microprocessor chip. In addition, prior microprocessor chips may include an on-chip memory such as an on-chip cache memory or an on-chip main memory.
Microprocessor chips having an on-chip cache memory are commonly employed in high performance computer systems. Such computer systems usually include a main memory contained in memory chips separate from the microprocessor chip. Such separate main memory chips can provide a large main memory for high performance applications.
In contrast, microprocessor chips having an on-chip main memory are commonly employed in low cost or portable computer systems. A microprocessor chip having an on-chip main memory usually limits the overall component count and cost of the system by eliminating the extra main memory chips.
Similarly, in the prior art, some memory chips are designed to operate as main memory chips and others are designed to operate as cache memory chips. Prior art memory chips are not reconfigurable to operate as either cache or main memory.
Typically, a manufacturer of such microprocessor chips undertakes a separate microprocessor design process for each type of microprocessor chip. Similarly, a manufacturer of memory chips undertakes a separate design for each type of memory chip. For example, chip layout and processing steps for a microprocessor with an on-chip cache memory usually differ from the chip layout and design steps for a microprocessor with an on-chip main memory. Similarly, the layout and design steps of a cache memory chip differs from the layout and design steps of a main memory chip. Unfortunately, such differing design processes typically increases the overall cost of such microprocessor and memory chips and extends time required to bring such chips to market. In addition, such extra design efforts usually increase the costs and complexities of chip testing and support.
SUMMARY OF THE INVENTION
A memory chip is disclosed having a memory which is reconfigurable as a main memory or as a cache memory. The memory chip may be a microprocessor chip having a memory reconfigurable to operate as a main memory or as a cache, or it may be a stand-alone memory chip that is thus reconfigurable. The chip is a product of a single chip design process and is suitable for application to a wide range of computer systems or computer-related device products.
Other features and advantages of the present invention will be apparent from the detailed description that follows.
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Bataille Pierre-Michel
Hewlett--Packard Development Company, L.P.
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