Microprocessor cache consistency

Details Microprocessor cache consistency Microprocessor cache consistency

1998-01-21

2000-10-24

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711138, 711144, G06F 1208, G06F 15167

Patent

active

061382167

ABSTRACT:
A method is described of managing memory in a microprocessor system comprising two or more processors (40, 42). Each processor (40, 42) has a cache memory (44, 46) and the system has a system memory (48) divided into pages subdivided into blocks. The method is concerned with managing the system memory (48) identifying areas thereof as being "cacheable", "non-cacheable" or "free". Safeguards are provided to ensure that blocks of system memory (48) cannot be cached by two different processors (40, 42) simultaneously.

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Brorsson M et al, "Characterising and Modelling Shared Memory Accesses in Multiprocessor Programs" Parallel Computing, vol. 22, No. 6, Sep. 1996, pp. 869-893.

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