Microprocessor burst mode data transfer ordering circuitry and m

Details Microprocessor burst mode data transfer ordering circuitry and m Microprocessor burst mode data transfer ordering circuitry and m

1997-02-26

1998-09-15

Swann, Tod R.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711100, 711118, 711130, 711147, 711154, G06F 1200, G06F 1300

Patent

active

058095144

ABSTRACT:
The present invention provides a method for transferring groups of data between a microprocessor cache memory (114) and an external memory (105) across a data bus (Bbus). Each group of data includes as many bits of data as the width of the bus (Bubs) with the total amount of data transferred filling a line in the cache memory (114). The bus interface unit (112) of the microprocessor (110) initiates a burst read by starting a read request, asserting the address strobe bit and sending the initial requested address on the external bus address bits of the microprocessor (110). The external system will then respond by asserting a burst ready signal, followed by the data bits residing in the appropriate address position. The particular addresses for this data is selected according to the current burst mode, which may be high performance, low power or compatible with a previously known burst mode. Subsequent groups of data are then sent in subsequent cycles according to the prescribed order of the burst mode up to n (=B/b) transfers. In a high performance mode the first group of bytes requested are always returned first. The next transfer will supply the necessary data that will satisfy the next level of data size hierarchy. Thereafter, transfer order follows an increasing wrap-around order. A low power mode includes an initial data order similar to the high performance mode with the additional limitation that only one address bit changes for each sequential data group. A burst write is performed similarly.

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