Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2007-08-14
2009-11-10
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S185170, C365S185180, C365S185240, C365S235000
Reexamination Certificate
active
07616507
ABSTRACT:
A memory system including a nonvolatile semiconductor memory device and a controller. The memory device includes a plurality of word lines; and a plurality of memory cells each connected to a corresponding one of the word lines and each having N threshold voltages for storing multi-valued level, where N is a natural number of 4 or greater; wherein stored data in each of the plurality of memory cells constitutes a plurality of pages, at least only a part of multi-value level is used for storing data, a data “1” is always written to a lower page, a “0” or “1” binary data is written to an upper page, the same data is written in each of the pages when writing in the nonvolatile memory device, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory device.
REFERENCES:
patent: 6259624 (2001-07-01), Nobukata
patent: 6356965 (2002-03-01), Broyles et al.
patent: 7170780 (2007-01-01), Kawai
patent: 7234052 (2007-06-01), Lee et al.
patent: 2003-271391 (2003-09-01), None
Sakaue Kenji
Sukegawa Hiroshi
Tsunoda Hitoshi
Kabushiki Kaisha Toshiba
Luu Pho M.
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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