Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-09-29
2001-08-14
Wiley, David (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S062000
Reexamination Certificate
active
06275886
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally directed to serial buses for computer systems, and more particularly, to a microprocessor-based interface arrangement for IEEE 1394 buses.
BACKGROUND OF THE INVENTION
The FireWire® serial bus architecture was originally developed by Apple Computer. The objectives that drove development of the FireWire serial bus were ease of use, high rate of data transfer, support for isochronous applications, very large memory mapped address space and others. The IEEE formalized the FireWire architecture in the IEEE 1394-1995 specification. This standard will be hereinafter referenced as the “IEEE 1394 standard” or just the “1394 standard.” A description of the IEEE 1394 system architecture is provided in the book, “FireWire System Architecture : IEEE 1394” by Don Anderson and published by MindShare, Inc., 1998. Details regarding the IEEE 1394 standard can be found in the “IEEE 1394-1995,” “IEEE 1394.A,” and “IEEE 1394.B” specifications, the contents of which are herein incorporated by reference.
Texas Instruments and other companies presently have a variety of chip sets for IEEE 1394 applications. The chip sets are generally comprised of either separate chips that implement the link and PHY layers of the 1394 standard, or a single chip that implements both the link and PHY layers. The link layer generally performs packet formatting for data to be transferred to and from a locally coupled host system, while the PHY layer provides the physical interface to the serial bus.
The commercially available chip sets are generally hardwired solutions that promote easy integration into specific applications. However, once the chip sets are integrated into a product, for example a digital camera, problems uncovered in the link/PHY chip set may be expensive to remedy. Furthermore, improvements in and extensions to the 1394 standard may make the chip set obsolete. Therefore, a link/PHY circuit arrangement that addresses the above identified problems is desirable.
SUMMARY OF THE INVENTION
The present invention is a microprocessor-based interface circuit arrangement for IEEE 1394 buses. In one embodiment, the circuit arrangement comprises a local bus to which are coupled a processor, a read-only memory circuit, a random access memory circuit, and a 1394 port interface circuit arrangement. The processor is configured and arranged to perform selected link layer functions of the IEEE 1394 standard. The read-only memory circuit is configured with instructions that cause the processor to perform the selected link layer functions. The random access memory circuit is arranged for storage of data manipulated by the link layer functions. The 1394 port interface circuit arrangement is arranged to couple to the 1394 standard serial bus and transfer data between the random access memory and the 1394 bus via the local bus responsive to the processor performing the selected link layer functions.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 6173348 (2001-01-01), Hewitt
patent: 6185622 (2001-02-01), Sato
Philips Semiconductor Inc.
Wiley David
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