Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1997-03-21
1998-10-13
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711169, 395309, 395287, G06F 1318
Patent
active
058227792
ABSTRACT:
A data processing technique with which a CPU core accesses memory devices over a bus. Some of the memory devices are on-chip, and some may be off-chip. In order to optimize its operation, the CPU core accesses the on-chip devices via a core buffer interface unit ("BIU") which has been tuned to on-chip operation. Off-chip devices communicate with the CPU core via a system BIU which translates the on-chip bus transactions to meet the off-chip device requirements.
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Baydatch Yair
Falik Ohad
Intrater Gideon
Ostrer Aharon
Sandbank Alberto
Bragdon Reginald G.
Chan Eddie P.
National Semiconductor Corporation
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