Microprocessor architecture capable of supporting multiple...

Details Microprocessor architecture capable of supporting multiple... Microprocessor architecture capable of supporting multiple...

2005-08-30

2010-02-02

Nguyen, Hiep T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

Reexamination Certificate

active

07657712

ABSTRACT:
A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor and the one or more memory ports of the processor. The memory control unit also includes a switch arbitration unit to arbitrate for the switch network, and a port arbitration unit to arbitrate for the one or more memory ports.

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