Microprocessor architecture capable of supporting multiple...

Details Microprocessor architecture capable of supporting multiple... Microprocessor architecture capable of supporting multiple...

1999-02-22

2001-08-07

Dinh, Dung C. (Department: 2153)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S116000, C710S244000, C710S041000, C711S151000, C711S158000, C712S029000

Reexamination Certificate

active

06272579

ABSTRACT:

The present application is related to the following applications, all assigned to the Assignee of the present application:
1. HIGH-PERFORMANCE RISC MICROPROCESSOR ARCHITECTURE, invented by Le Nguyen et al, SMOS-7984MCF/GBR, application Ser. No. 07/727,066, filed Jul. 8, 1991, now abandoned;
2. EXTENSIBLE RISC MICROPROCESSOR ARCHITECTURE, invented by Quang Trang et al, SMOS-7985MCF/GBR, application Ser. No. 07/727,058, filed Jul. 8, 1991, now abandoned;
3. RISC MICROPROCESSOR ARCHITECTURE WITH ISOLATED ARCHITECTURAL DEPENDENCIES, invented-by Yoshi Miyayama, SMOS-7987MCF/GBR/RCC, application Ser. No. 07/726,744, filed Jul. 8, 1991, now abandoned;
4. RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING MULTIPLE TYPED REGISTER SETS, invented by Sanjiv Garg, SMOS-7988MCF/GBR/RCC, application Ser. No. 07/726,773, filed Jul. 8, 1991, now U.S. Pat. No. 5,493,687;
5. RISC MICROPROCESSOR ARCHITECTURE IMPLEMENTING FAST TRAP AND EXCEPTION STATE, invented by Quang Trang et al, SMOS-7989MCF/GBR/WSW, application Ser. No. 07/726,942, filed Jul. 8, 1991, now abandoned;
6. SINGLE CHIP PAGE PRINTER CONTROLLER, invented by Derek J. Lentz, SMOS-7991MCF/GBR/HKW, application Ser. No. 07/726,929, filed Jul. 8, 1991, now abandoned.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessor architecture in general and in particular to a microprocessor architecture capable of supporting multiple heterogeneous microprocessors.
2. Description of the Related Art
A computer system comprising a microprocessor architecture capable of supporting multiple processors typically comprises a memory, a memory system bus comprising data, address and control signal buses, an input/output I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. The I/O devices may comprise, for example, a direct memory access (DMA) controller-processor, an ethernet chip, and various other I/O devices. The microprocessors may comprise, for example, a plurality of general purpose processors as well as special purpose processors. The processors are coupled to the memory by means of the memory system bus and to the I/O devices by means of the I/O bus.
To enable the processors to access the MAU and the I/O devices without conflict, it is necessary to provide a mechanism which assigns a priority to the processors and I/O devices. The priority scheme used may be a fixed priority scheme or a dynamic priority scheme which allows for changing priorities on the fly as system conditions change, or a combination of both schemes. It is also important to provide in such a mechanism a means for providing ready access to the memory and the I/O devices by all processors in a manner which provides for minimum memory and I/O device latency while at the same time providing for cache coherency. For example, repeated use of the system bus to access semaphores which are denied can significantly reduce system bus bandwidth. Separate processors cannot be allowed to read and write the same data unless precautions are taken to avoid problems with cache coherency.
SUMMARY OF THE INVENTION
In view of the foregoing, a principal object of the present invention is a computer system comprising a microprocessor architecture capable of supporting multiple heterogenous processors which are coupled to multiple arrays of memory and a plurality of I/O devices by means of one or more I/O buses. The arrays of memory are grouped into subsystems with interface circuits known as Memory Array Units or MAU's. In each of the processors there is provided a novel memory control unit (MCU). Each of the MCU's comprises a switch network comprising a switch arbitration unit, a data cache interface circuit, an instruction cache interface circuit, an I/O interface circuit and one or more memory port interface circuits known as ports, each of said port interface circuits comprising a port arbitration unit.
The switch network is a means of communication between a master and a slave device. To the switch, the possible master devices are a D-cache, an I-cache, or an I/O controller unit (IOU) and the possible slave devices are a memory port or an IOU.
The function of the switch network is to receive the various instructions and data requests from the cache controller units (CCU) (I-cache, D-cache) and the IOU. After having received these requests, the switch arbitration unit in the switch network and the port arbitration unit in the port interface circuit prioritizes the requests and passes them to the appropriate memory port (depending on the instruction address). The port, or ports as the case may be, will then generate the necessary timing signals, receive or send the necessary data to/from the MAU. If it is a write (WR) request, the interaction between the port and the switch stops when the switch has pushed all the write data into the write data FIFO (WDF) from the switch. If it is a read (RD) request, the interaction between the switch and the port only ends when the port has sent the read data back to the requesting master through the switch.
The switch network is composed of four sets of tri-state buses that provide the connection between the cache, IOU and the memory ports. The four sets of tri-state buses comprise SW_REQ, SW_WD, SW_RD and SW_IDBST. In a typical embodiment of the present invention, the bus SW_REQ comprises 29 wires which is used to send the address, ID and share signal from a master device to a slave device. The ID is a tag associated with a memory request so that the requesting device is able to associate the returning data with the correct memory address. The share signal is a signal indicating that a memory access is to shared memory. When the master device is issuing a request to a slave, it is not necessary to send the full 32 bits of address on the switch. This is because in a multimemory port structure, the switch would have decoded the address and would have known whether the request was for memory port
0
, port
1
or the IOU, etc. Since each port has a pre-defined memory space allotted to it, there is no need to send the full 32 bits of address on SW_REQ.
In practice, other request attributes such as, for example, a function code and a data width attribute are not sent on the SW_REQ because of timing constraints. If the information were to be carried over the switch, it would arrive at the port one phase later than needed, adding more latency to memory requests. Therefore, such request attributes are sent to the port on dedicated wires so that the port can start its state machine earlier and thereby decrease memory latency.
Referring to
FIG. 8
, the bus SW_WD comprises 32 wires and is used to send the write data from the master device (D-cache and IOU) to the FIFO at the memory port. It should be noted that the I-cache reads data only and does not write data. This tri-state bus is “double-pumped” which means that a word of data is transferred on each clock phase, reducing the wires needed, and thus the circuit costs. WD
00
, WD
01
, WD
10
and WD
11
are words of data. Since the buses are double-pumped, care is taken to insure that there is no bus conflict when the buses turn around and switch from a master to a new master.
Referring to
FIG. 9
, the bus SW_RD comprises 64 wires and is used to send the return read data from the slave device (memory port and IOU) back to the master device. Data is only sent during one phase
1
. This bus is not double-pumped because of timing constraints of the caches in that the caches require that the data be valid at the falling edge of CLK
1
. Since the data is not available from the port until phase
1
when clock
1
is high, if an attempt were made to double-pump the SW_RD bus, the earliest that a cache would get the data is at the positive edge of CLK
1
and not the negative edge thereof. Since bus SW_RD is not double-pumped, this bus is only active (not tri-stated) during phase
2
. There is no problem with bus driver conflict when the bus switches to a different master.
The bus SW_IDBST comprises four wir

Affiliated with

Also associated with

Rating

Microprocessor architecture capable of supporting multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor architecture capable of supporting multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor architecture capable of supporting multiple... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2488489