Boots – shoes – and leggings
Patent
1981-06-08
1984-08-21
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 918
Patent
active
044674139
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to digital data processing. More particularly, the invention relates to microprocessor data exchange apparatus.
U.S. Pat. No. 4,020,472, issued Apr. 26, 1977, discloses a microprocessor data exchange apparatus which comprises a plurality of data exchange units having first multichannel inputs/outputs combined with external bidirectional data buses, a register unit having bidirectional inputs/outputs connected to internal bidirectional data buses attached to second multichannel inputs/outputs of data exchange units belonging to another plurality.
The known apparatus also comprises a control unit having multichannel outputs coupled to control inputs of the data exchange units and the register unit, having a multichannel input connected to a microinstruction bus, an input coupled to a triggering line, and an input/output connected to a clock line.
The known apparatus provides a slow transfer of both a data set of a given length and a single information byte, and cannot handle or analyze data during exchange.
SUMMARY OF THE INVENTION
The principal object of the invention is to provide microprocessor data exchange apparatus having a considerable speed increase in transferring both a data set of a given length and a single information byte and also processing and analysis of data in the course of exchange due to the availability of new units and links.
This object is attained by the microprocessor data exchange apparatus of the invention, comprising two pluralities of data exchange units having first multichannel inputs/outputs coupled to external bidirectional data buses. A register unit has bidirectional inputs/outputs coupled to internal bidirectional data buses which connect second multichannel inputs/outputs of the data exchange units of a first of the two pluralities. A control unit has a multichannel output connected to control inputs of the data exchange units of the two pluralities and the register unit, a multichannel input coupled to a microinstruction bus, a first input coupled to a triggering line, and also an input/output connected to a clock bus. In accordance with the invention, a data processing unit is provided for converting information in the course of exchange a counter has inputs/outputs coupled, together with a multichannel input group of the data processing/converting unit, to the internal bidirectional data buses. A multichannel output of the counter is applied to a multichannel input of the data processing/converting unit.
The apparatus also includes a switch adapted to change the direction of data flow. The switch has a first group of multichannel inputs/outputs coupled to the internal bidirectional buses, and a second group of multichannel inputs/outputs coupled to a second multichannel inputs/outputs of the data exchange units of a second of the two pluralities. The first multichannel inputs of the switch are coupled to multichannel outputs of the data processing unit.
Besides, there is also provided a conditional operation unit for generating processed information tags having an input/output coupled to an external line, multichannel inputs/output coupled to the internal bidirectional data buses, a multichannel input connected to the microinstruction bus, four inputs coupled respectively to the outputs of the register unit, the counter, the data processing/converting unit and the switch, and an output coupled to a second input of the control unit. Multichannel inputs/outputs of the control unit are coupled to the internal bidirectional data buses and its multichannel output is coupled to respective control inputs of the counter, the data processing/converting unit, the switch, and the conditional operation unit.
The register unit preferably comprises a storage register and a shift register, multichannel inputs/outputs of these registers being coupled to the internal bidirectional information buses. An output of the most significant bit of the shift register is connected to a respective input of the conditional operation un
REFERENCES:
patent: 4020472 (1977-04-01), Bennett et al.
patent: 4086627 (1978-04-01), Bennett et al.
Chicherin Jury E.
Dshkhunian Valery L.
Kovalenko Sergei S.
Mashevich Pavel R.
Telenkov Vyacheslav V.
Shaw Gareth D.
Wiens Tim A.
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