Microprocessor apparatus and method for optimizing block...

Electrical computers and digital processing systems: support – Data processing protection using cryptography – Computer instruction/address encryption

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C713S189000, C713S191000

Reexamination Certificate

active

07392400

ABSTRACT:
The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction and translation logic. The cryptographic instruction is received by fetch logic in a microprocessor as part of an instruction flow. The cryptographic instruction prescribes one of the cryptographic operations. The translation logic translates the cryptographic instruction into micro instructions. The micro instructions are ordered to direct the microprocessor to load a second input text block and to execute the one of the cryptographic operations on the second input text block prior to directing the microprocessor to store an output text block corresponding to a first input text block. Consequently, the output text block is stored during execution of the one of the cryptographic operations on the second input text block.

REFERENCES:
patent: 4168396 (1979-09-01), Best
patent: 4250546 (1981-02-01), Boney et al.
patent: 4278837 (1981-07-01), Best
patent: 4316055 (1982-02-01), Feistel
patent: 4319079 (1982-03-01), Best
patent: 4386234 (1983-05-01), Ehrsam et al.
patent: 4465901 (1984-08-01), Best
patent: 4633388 (1986-12-01), Chiu
patent: 4888802 (1989-12-01), Cooney
patent: 5016276 (1991-05-01), Matumoto et al.
patent: 5134713 (1992-07-01), Miller et al.
patent: 5218637 (1993-06-01), Angebaud et al.
patent: 5633934 (1997-05-01), Hember
patent: 5666411 (1997-09-01), McCarty
patent: 5673319 (1997-09-01), Bellare et al.
patent: 5828873 (1998-10-01), Lynch
patent: 5870470 (1999-02-01), Johnson et al.
patent: 6006328 (1999-12-01), Drake
patent: 6026490 (2000-02-01), Johns-Vano et al.
patent: 6081884 (2000-06-01), Miller
patent: 6182216 (2001-01-01), Luyster
patent: 6246768 (2001-06-01), Kim
patent: 6269163 (2001-07-01), Rivest et al.
patent: 6301362 (2001-10-01), Matyas, Jr. et al.
patent: 6324286 (2001-11-01), Lai et al.
patent: 6578150 (2003-06-01), Luyster
patent: 6674874 (2004-01-01), Yoshida et al.
patent: 6789147 (2004-09-01), Kessler et al.
patent: 6919684 (2005-07-01), Brandes
patent: 6983374 (2006-01-01), Hashimoto et al.
patent: 7073059 (2006-07-01), Worely et al.
patent: 7088826 (2006-08-01), Houlberg et al.
patent: 7110545 (2006-09-01), Furuya et al.
patent: 7124302 (2006-10-01), Ginter et al.
patent: 7184549 (2007-02-01), Sorimachi et al.
patent: 7194090 (2007-03-01), Muratani et al.
patent: 2001/0037450 (2001-11-01), Metlitski et al.
patent: 2001/0050989 (2001-12-01), Zakiya
patent: 2002/0101985 (2002-08-01), CaMgnac et al.
patent: 2002/0162026 (2002-10-01), Neuman et al.
patent: 2002/0191784 (2002-12-01), Yup et al.
patent: 2003/0039354 (2003-02-01), Kimble et al.
patent: 2003/0202658 (2003-10-01), Verbauwhede
patent: 2003/0223580 (2003-12-01), Snell
patent: 2004/0047466 (2004-03-01), Feldman et al.
patent: 2005/0084076 (2005-04-01), Dhir et al.
patent: 1309351 (2001-08-01), None
patent: 1431584 (2003-07-01), None
patent: 3432721 (1986-03-01), None
patent: 0913767 (1999-05-01), None
patent: 1202150 (2002-05-01), None
patent: 1215842 (2002-06-01), None
patent: 1271839 (2003-01-01), None
patent: 1298518 (2003-04-01), None
patent: 1351432 (2003-10-01), None
patent: 57176457 (1982-10-01), None
patent: WO0076119 (2000-12-01), None
patent: WO0117152 (2001-03-01), None
patent: WO0144900 (2001-06-01), None
patent: WO0184769 (2001-11-01), None
patent: WO03036508 (2003-05-01), None
Fast DDP-based ciphers: from hardware to software Goots, N.D.; Moklovyan, N.A.; Moldovyanu, P.A.; Summerville, D.H.; Circuits and Systems, 2003. MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium on vol. 2, Dec. 27-30, 2003 pp. 770-773 vol. 2.
First step toward Internet based embedded control system Suwartadi, E.; Gunawan, C.; Setijadi, A.; Machbub, C.; Control Conference, 2004. 5th Asian vol. 2, Jul. 20-23, 2004 pp. 1226-1231 vol. 2.
High-throughput reconfigurable computing: design and implementation of an IDEA encryption cryptosystem on the SRC-6E reconfigurable computer; Michalski, A.; Buell, D.; Gaj, K.; Field Programmable Logic and Applications, 2005. International Conference on Aug. 24-26 2005 pp. 681-686.
“IBM PCI Cryptographic Coprocessor CCA Basic Services Reference and Guide for IBM 4758 Models 002 and 023 with Release 2.40,” IBM, Sep. 2001, XP002291430.
Schneier: “Applied Cryptography.” 1996. John Wiley & Sons, New York, US. XP002341498. pp. 30-31, pp. 189-211, pp. 446-459.
Schneier. “Applied Cryptography, Protocols, Algorithms and Source Code In C.” 2nd edition 2.3 One Way Funtions Applied Cryptography. Oct. 18, 1995. pp. 29-31, 193. XP002224472.
Rechenberg et al. “Informatik-Handbuch” Informatik-Handbuch, 2002, XP0023666659. pp. 304-pp. 324.
Institute for applied information processing and communications, Tu Graz: “Cryptographic Logic Unit /Crypto Unit Mac Macrocell Webpages.” Cryptographic Reduced instruction Set Processor Smartcard, online Apr. 12, 2000. XP00236660 Retrieved from the Internet: URL: http://web.archive.org/web/20000412010535 http://www.iaik.tu-graz.ac.at/Research/VLSI/CRISP/crisp.htm retrieved on Feb. 7, 2006! p. 8.
“Secure Microcontrollers for Smart Cards. AT90SC Summary” Announcement Atmel. 1999, pp. 1-7. XP002291271.
Ulmann, B. “Designing a Nice Processor.” Microprocessors and Microsystems, IPC Business Press LTD. London, GB. vol. 23, No. 5. Oct. 25, 1999. pp. 257-264. XP004321479 ISSN: 0141-9331.
Wu et al. “CryptoManiac: a fast flexible architecture for secure communication.” Proceedings of the 28th. International Symposium on Computer Architecture. ISCA 2001. Jun. 30, 2001 pp. 104-113, XP010553867.
Gladman, Brian. “A Specification for Rijndael, the AES Algorithm.”Online. Mar. 13, 2003. XP002376287.
Backhus E. “AES in FPGAS Implementierung Des Advanced Encryption Standards in Hardware.” Elektronik, WEKA Fachzeitschriftenverlag, Poing, DE. vol. 52, No. 8. Apr. 15, 2003 pp. 54-56, 58, 60. XP001160048.
Daemon J et al. “AES Proposal: Rijndael.” AES Proposal Sep. 3, 1999. pp. 1-45, XP001060386.
Tong et al. “A system level Implementation of Rijndael on a memory-slot based FPGA card.” Field-Programmable Technology, 2002. (FPT). Dec. 16, 2002, pp. 102-109, XP010636515 ISBN: 0-7803-7574-2.
Taylor D E et al. “Dynamic Hardware Plugins: Exploiting Reconfigurable Hardware for High-Performance Programmable Routers.” Computer Networks, Elsevier Science Publishers B.V., Amsterdam, NL, vol. 38, No. 3. Feb. 21, 2002 pp. 295-310. XP004333786. ISSN: 1389-1286.
Elbirt A J et al. “Instruction-Level Distributed Processing for Symmetric-Key Cryptography.” Parallel and Distributed Processing Symposium. 2003, Apr. 22, 2003. pp. 78-87. XP010645610 ISBN: 0-7695-1926-1.
McKinnon et al. “A Configurable Middleware Framework with Multiple Quality of Service Properties for Small Embedded Systems.” Network Computing And Applications, 2003. NCA 2003. Second IEEE International Symposium On Apr. 16-18 2003, Piscataway, NJ. USA IEEE, Apr. 16, 2003. pp. 197-204, XP010640251 ISBN: 0-7695-1938-5.
Lee et al. “Efficient Permutation Instructions for Fast Software Cryptography.” IEEE Micro, Nov. 2001. pp. 56-69.
Dimond et al. “Application-specific Customisation of Multi-Threaded Soft Processors.” Computers and Digital Techniques. IEEE Proceedings. vol. 153, Issue 3. May 2, 2006. pp. 173-180.
Anderson et al. “Cryptographic Processors—A Survey.” Proceedings of the IEEE. vol. 94, Issue 2. Feb. 2006. pp. 357-369.
Eberle et al. “Architectural Extensions for Elliptic Curve Cryptography over GF(2μ) on 8-bit Microprocessors.” Application-Specific Systems. Architecture Processors. 2005. ASAP 2005. 16th IEEE International Conference on Jul. 23-25, 2005. pp. 343-349.
Kuhn, Markus G. “Cipher Instruction Search Attack on the Bus-Encrypt

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Microprocessor apparatus and method for optimizing block... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microprocessor apparatus and method for optimizing block..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor apparatus and method for optimizing block... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2801184

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.