Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-08
2006-08-08
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S144000, C711S145000
Reexamination Certificate
active
07089368
ABSTRACT:
A microprocessor apparatus for exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block prefetch instruction into a micro instruction sequence directing a microprocessor to prefetch a specified number of cache lines, where the extended block prefetch instruction is encoded to direct the microprocessor to prefetch the specified number of cache lines in the exclusive state. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the specified number of cache lines in the exclusive state, where the specified number of cache lines includes data entities that are to be subsequently modified, and where prefetching the specified numbers of cache lines in the exclusive state occurs parallel with execution of program instructions prior to execution of subsequent store instructions that direct the microprocessor to modify the data entities.
REFERENCES:
patent: 4959777 (1990-09-01), Holman, Jr.
patent: 5742785 (1998-04-01), Stone et al.
patent: 5903911 (1999-05-01), Gaskins
patent: 5944815 (1999-08-01), Witt
patent: 5966734 (1999-10-01), Mohamed et al.
patent: 6018763 (2000-01-01), Hughes et al.
patent: 6088789 (2000-07-01), Witt
patent: 6253306 (2001-06-01), Ben-Meir et al.
patent: 6460132 (2002-10-01), Miller
patent: 6470444 (2002-10-01), Sheaffer
patent: 2001/0014932 (2001-08-01), Sugaruma
patent: 2001/0021963 (2001-09-01), Cypher
patent: 2001/0037419 (2001-11-01), Hagersten
patent: 2001/0037434 (2001-11-01), Hughes et al.
patent: 2002/0007443 (2002-01-01), Gharachorloo et al.
patent: 2002/0035876 (2002-03-01), Freersken et al.
patent: 2002/0141152 (2002-10-01), Pokhama
patent: 2003/0131218 (2003-07-01), Mayfield et al.
patent: 2003/0188129 (2003-10-01), Henry et al.
patent: 11765433 (1998-03-01), None
patent: 0489556 (1992-06-01), None
patent: 0825538 (1998-02-01), None
patent: 0947919 (1999-10-01), None
patent: 1353267 (2003-10-01), None
Tullsen et al: “Effective Cache Prefetching on Bus Based Multiprocessors,” ACM Transactions on Computer Systems, Association for Computing Machinery. New York, US, vol. 13, No. 1, Feb. 1, 1995, pp. 57-88.
Mowry et al: “Tolerating Latency Through Software-Controlled Prefetching in Shared-Memory Multiprocessors,” Journal of Parallel and Distributed Computing, Academic Press, Duluth, MN, US, vol. 12, No. 2, Jun. 1, 1991, pp. 87-106.
Milenkovic, A: “Achieving High Performance in Bus-Based Shared-Memory Mulitiprocessors,” IEEE Concurrency, IEEE Service Center, Piscataway, NY, US, vol. 8, No. 3, Jul. 2000, pp. 36-44.
Todd Mowry, “Tolerating Latency Through Software-Controlled Data Prefetching,” May 1994, pp. i-iv and pp. 174-175.
Todd Mowry, “Tolerating Latency Through Software-Controlled Data Prefetching,” May 1994, pp. I-Iv and pp. 174-175.
Elmore Reba I.
Huffman James W.
Huffman Richard K.
IP-First LLC
LandOfFree
Microprocessor apparatus and method for exclusively... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microprocessor apparatus and method for exclusively..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor apparatus and method for exclusively... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3665405