Microprocessor apparatus and method for exclusive prefetch...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S141000, C711S144000, C711S145000

Reexamination Certificate

active

07080210

ABSTRACT:
A microprocessor apparatus that enables exclusive prefetch of a cache line from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended prefetch instruction into a micro instruction sequence that directs a microprocessor to prefetch a cache line in an exclusive state, where the extended prefetch instruction is encoded to direct the microprocessor to prefetch the cache line in the exclusive state. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues a transaction over a memory bus that requests the cache line in the exclusive state, where the cache line comprises a data entity that is to be subsequently modified, and where prefetching the cache line in the exclusive state occurs in parallel with execution of program instructions prior to execution of a subsequent store instruction that directs the microprocessor to modify the data entity.

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