Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1997-06-03
2002-06-04
Beausoleil, Robert (Department: 2181)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S002000, C713S100000
Reexamination Certificate
active
06401197
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microprocessor having a reset function and, more particularly, to a microprocessor having a simple mechanism required to initialize a system, especially when used in a multiprocessor system.
The present invention also relates to a multiprocessor system having a simple mechanism for initializing the entire system.
2. Description of the Background Art
A microprocessor performs a reset action for initializing the inside of the processor in response to assertion of a reset signal from the exterior upon power-on for execution of a user program, for example. The reset action includes a hardware reset action wherein the reset signal asserted from the exterior of the microprocessor is applied to memory elements in the processor to reset the contents stored in the memory elements, and a software reset action wherein a program for reset fetched from an external memory is executed in the processor to allow the user program to be ready for processing. Particularly, in the software reset action, when the reset signal is asserted, a reset vector entry is fetched from the external memory, and information contained in the entry is referred to, whereby the program for reset is fetched.
In a multiprocessor system including a plurality of processors for performing the above described reset action in such a manner that one of the processors functions as a master processor while the others function as slave processors, all of the processors must be initialized to reset the entire system. For this purpose, the reset signal is initially asserted in all of the processors. A program for reset is previously stored in a read only memory (referred to hereinafter as a ROM) on the system. After assertion of the reset signal, each of the processors accesses the ROM to execute the program for reset, whereby each processor is initialized. Since the processors are not permitted to simultaneously access the ROM, the multiprocessor system is adapted such that the processors access the ROM in sequential order.
In the multiprocessor system constructed as above described, if the reset signal is simultaneously asserted in the processors, the processors are not permitted to simultaneously access the ROM which stores the reset vector entry in order to refer to the reset vector entry. Thus, a new complicated mechanism is required such as a bus adjustment circuit for causing the plurality of processors to sequentially access the ROM. Further, it is a customary practice that the respective processors execute different program routines in the program for reset because of a difference in reset contents between the master and slave processors. Then, there arises a need for a mechanism for identifying which processor is to execute each of the program routines.
An alternative attempt considered is such that a plurality of local ROMs are provided in corresponding relation to the respective processors in the multiprocessor system and each of the processors executes the instruction for reset stored in the corresponding ROM to perform the reset action. However, this attempt involves a need to provide to each processor address information for specifying which one of the ROMs is accessed by each processor after the assertion of the reset signal. To meet this requirement, separate reset vector entries are considered to be set for the respective processors. However, the use of identical processors as the master and slave processors necessitates the setting of address information indicating the ROMs to be accessed by the respective processors for the reset vector entries from the exterior. In both ways, a mechanism for setting the address information from the exterior must be additionally provided. Further, the provision of the plurality of ROMs corresponding to the respective processors increases the amount of hardware.
The multiprocessor system requires a complicated mechanism for controlling processing between units such as the master processor and the slave processors. The provision of the above described new mechanism causes a more complicated system structure, and a multiplicity of memories are required to function the multiprocessor system. Thus, the unnecessary increase in the number of memories is not desirable.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a microprocessor comprises: a processing portion including an instruction decoder for decoding an instruction, the processing portion for performing various processes in accordance with a result of decoding from the instruction decoder to execute the instruction; an access control portion controlled by the processing portion for outputting an address specifying a memory area to apply the instruction stored in the memory area to the instruction decoder; and wherein memory elements in the microprocessor are reset in response to an external reset signal, and wherein, in a first mode, (i) a first interrupt process program is stored in the internal memory after completion of assertion of the reset signal, (ii) the processing portion controls the access control portion so that instructions constituting the first interrupt process program are applied to the instruction decoder in response to an interrupt signal applied to the processing portion, and (iii) the processing portion executes an instruction for reset among the instructions constituting the first interrupt process program applied to the instruction decoder, whereby the microprocessor is initialized.
Preferably, the microprocessor further comprises: an address terminal for outputting the address to the exterior, wherein the address terminal is in a high-impedance state in the first mode during the time between input of the reset signal and input of at least the interrupt signal.
Preferably, in the microprocessor, the access control portion outputs an information signal to the processing portion in response to a request from the processing portion that the access control portion should perform an access to the exterior of the microprocessor when the address terminal is in the high-impedance state, the information signal providing information about prohibition of the access.
Preferably, the microprocessor further comprises: an internal memory; and an internal data bus for establishing a connection between the internal memory and the processing portion, wherein the access control portion outputs the address to the internal memory so that the first interrupt process program is applied from the internal memory through the internal data bus to the instruction decoder.
According to a second aspect of the present invention, the microprocessor of the first aspect further comprises: mode setting means for setting the microprocessor in one of the first mode and a second mode, wherein, in the second mode, (iv) the processing portion controls the access control portion so that instructions constituting a reset process program are applied to the instruction decoder in response to the reset signal applied to the processing portion, (v) the processing portion executes the instructions of the reset process program applied to the instruction decoder, whereby the microprocessor is initialized, and (vi) interrupt data on which the interrupt signal is based are produced.
Preferably, in the microprocessor, the access control portion outputs the address to external memory means so that the reset process program stored in the external memory means is fetched and applied to the instruction decoder when the second mode is set.
Preferably, in the microprocessor, further comprising an internal memory and in the second mode, (vii) the reset process program is executed whereby a second interrupt process program is stored in the internal memory after completion of assertion of the reset signal.
Preferably, in the microprocessor, the first interrupt process program includes a process in accordance with a factor of the interrupt signal.
According to a third aspect of the present invention, a microprocessor comprises: first and secon
Beausoleil Robert
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Vo Tim
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