Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1995-12-28
1999-11-02
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
39550005, G06F 1100
Patent
active
059789379
ABSTRACT:
A microprocessor 10 has a processor core 20 and a debug module 30. The processor core 20 executes a user program and a monitor program for debugging a user target system 70. The debug module 30 serves as an interface with a debug tool 60, to let the processor core 20 execute the monitor program stored in the debug tool 60. The debug module 30 makes an interrupt or exception request to switch the processor core 20 from the user program to the monitor program.
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Miyamori Takashi
Yano Tatsuo
Beausoliel, Jr. Robert W.
Hewlett-Packard Co.
Iqbal Nadeem
Kabushiki Kaisha Toshiba
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