Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-03-28
2004-05-25
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S132000, C711S137000
Reexamination Certificate
active
06742102
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based on the prior Japanese Patent Application Laid-open No. 88972/2000, filed Mar. 28, 2000 in Japan by claiming priority under the Paris Convention.
BACKGROUND OF THE INVENTION
(i) Field of the Invention
The present invention relates to a microprocessor provided with a cache memory, and more particularly, it relates to a technique for suppressing reduction in performance caused due to a cache miss.
(ii) Description of the Related Art
In recent years, the speedup of a microprocessor is remarkable, and a difference in operating frequency between an external memory and a processor tends to be large. Therefore, reduction in performance due to access by the external memory has a great influence on the performance of the processor. In order to solve such a problem, there are released a large number of processors having a mechanism for including or adding a cache memory.
When a cache miss occurs, however, data must be obtained from a secondary cache memory or external memory which takes a time for accessing, and hence the processing performance is greatly reduced as compared with a case of a cache hit. In order to suppress reduction in the processing performance at the time of a cache miss, there is proposed a processor having a pre-fetch function.
A pre-fetch command is a command for loading the content of a designated memory into a cache memory, and most of the pre-fetch commands are explicitly issued by an order. By first refilling data which will be required after this command to the cache memory, the command which uses the data can be executed without causing any cache miss if cache refilling is completed in a period between the pre-fetch command and actual use of the data.
In regard to issue of the pre-fetch command, however, there is no best algorithm in the actual condition. In order to hold a cache line for the pre-fetch, it is often the case that any other cache line must be expelled from the cache. At this time, reduction in the performance may possibly occur depending on a frequency and a timing for issuing the pre-fetch. For example, a cache line having data which is often used is expelled by the pre-fetch or expelled by the following pre-fetch before the pre-fetched data is used.
SUMMARY OF THE INVENTION
In view of the above-described problems, it is an object of the present invention to provide a microprocessor capable of suppressing reduction in performance caused due to a cache miss when a specific command is issued.
To achieve this aim, according to the present invention, there is provided a microprocessor comprising:
a cache memory for storing temporarily storing data to be written in an external memory or data read from the external memory;
a variation obtaining portion for obtaining a variation of a value of a register used for a specific application from history information or a subsequent command when a specific command is issued; and
a cache refilling portion for executing refilling processing with respect to at least a part of a data area in the cache memory based on the obtained variation.
According to the present invention, when a specific command such as a subroutine call is issued, the refilling processing for the cache memory is executed based on a variation of a value of the register used for a specific application such as a stack pointer, and it is hence possible to reduce the cache miss penalties when executing the specific command.
In particular, the pre-fetch, issue of which command is said to be difficult, is not controlled by hardware, but a stack register whose application is special and whose rewrite timing can be readily predicted by hardware is used. Therefore, a destination of the pre-fetch can be dynamically and accurately predicted, thereby reducing cache miss penalties.
Further, when localization of data in a stack area is called into play and the data does not have to be refilled in the cache, it is set so that the external memory access which is not necessary at the time of pre-fetching data does not occur, and it is thus possible to realize a cache management mechanism which is suitable for a characteristic of the data.
Furthermore, there is provided a microprocessor comprising:
a cache memory for temporarily storing data to be written in an external memory or data read from the external memory;
a next pointer value calculator for calculating a value of a next stack pointer set in a subroutine when a command concerning a call for the subroutine is detected;
a pre-fetch requesting portion for requesting pre-fetch to the cache memory when the command concerning a call for the subroutine is detected; and
a cache controller for executing refilling processing of data in units of cache line of the cache memory by using a value calculated by the next pointer value calculator as a starting point when the pre-fetch is requested.
Moreover, there is provided the microprocessor including a cache memory for temporarily storing data to be written in an external memory or data read from the external memory, comprising:
a stack pointer calculator for increasing/decreasing a value of a stack pointer from a value of the stack pointer immediately before the subroutine is called by an amount corresponding to a size of a cache line of the cache memory;
a pre-fetch requesting portion for requesting pre-fetch to the cache memory when a command concerning a call for the subroutine is detected; and
a cache controller for executing refilling processing of data by using a value calculated by the stack pointer value calculator as a starting point when the pre-fetch is requested.
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Kabushiki Kaisha Toshiba
Portka Gary
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