Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-21
2006-11-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07139876
ABSTRACT:
A stack cache memory in a microprocessor and apparatus for performing fast speculative pop instructions is disclosed. The stack cache stores cache lines of data implicated by push instructions in a last-in-first-out fashion. An offset is maintained which specifies the location of the newest non-popped push data within the cache line stored in the top entry of the stack cache. The offset is updated when an instruction is encountered that updates the stack pointer register. When a pop instruction requests data, the stack cache speculatively provides data specified by the offset from the top entry to the pop instruction, before determining whether the pop instruction source address matches the address of the data provided. If the source address and the address of the data provided are subsequently determined to mismatch, then an exception is generated to provide the correct data.
REFERENCES:
patent: 3401376 (1968-09-01), Barnes et al.
patent: 3810117 (1974-05-01), Healey
patent: 5043870 (1991-08-01), Ditzel et al.
patent: 5500950 (1996-03-01), Becker et al.
patent: 5751990 (1998-05-01), Krolak et al.
patent: 5930820 (1999-07-01), Lynch
patent: 5953741 (1999-09-01), Evoy et al.
patent: 5956752 (1999-09-01), Mathews
patent: 5960467 (1999-09-01), Mahalingaiah et al.
patent: 6009499 (1999-12-01), Koppala
patent: 6038643 (2000-03-01), Tremblay et al.
patent: 6151661 (2000-11-01), Adams et al.
patent: 6275903 (2001-08-01), Koppala et al.
patent: 6415380 (2002-07-01), Sato
patent: 6425055 (2002-07-01), Sager et al.
patent: 6532531 (2003-03-01), O'Connor et al.
patent: 6622211 (2003-09-01), Henry et al.
patent: 6671196 (2003-12-01), Civlin
patent: 2002/0144061 (2002-10-01), Faanes et al.
patent: 2004/0133886 (2004-07-01), Wu
patent: 2004/0188959 (2004-09-01), Kawamoto
patent: 1391167 (2003-01-01), None
patent: 2260429 (1993-04-01), None
patent: 2307319 (1997-05-01), None
“Dual On-Chip Instruction Cache Organization in High Speed Processors.”IBM Technical Disclosure Bulletin. IBM Corp, New York, US. vol. 37, No. 12, Dec. 1994, pp. 213-214.
(In the file SCreport.pdf): Implementing a Stack Cache; Hensath, Morton, Sjodin; obtained from http://www.owlnet.rice.edu/˜elec525/projects/SCreport.pdf; accessed on Aug. 13, 2003.
(In the file JavaStack Cache.doc); Design Issues—Stack Cache; obtained from http://murray.newcastle.edu.au/users/students/1999/c9510422/design1.html; http://murray.newcastle.edu.au/users/students/1999/c9510422/design2.html; http://murray.newcastle.edu.au/users/students/1999/c9510422/design3.html; http://murray.newcastle.edu.au/users/students/1999/c9510422/design4.html; http://murray.newcastle.edu.au/users/students/1999/c9510422/architecture.html; accessed on Dec. 2, 2003.
(In the fine AMD Hammer micro architecture.pdf): AMD's Hammer micro architecture; http://chip-architect.com
ews/hammer.jpg; accessed on Aug. 29, 2002.
Dare Ryan A.
Davis E. Alan
Huffman James W.
IP-First LLC
Kim Matthew
LandOfFree
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