Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-11-06
2003-04-22
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S122000, C711S126000, C711S128000, C711S205000, C711S206000, C711S207000, C700S200000
Reexamination Certificate
active
06553477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microprocessor and an address translation method for the microprocessor.
2. Description of the Related Art
In a computer employing a virtual memory system, translation from a virtual address to a physical address must be dynamically performed, on a page-by-page basis, during program execution. The hardware mechanism for implementing this address translation is called the dynamic address translator (DAT). The DAT performs the address translation by referring to a table called the address translation table or page table. The address translation table, which is provided within main memory and is managed by an operating system (OS), is a table that indicates, for example, which virtual page number corresponds to which physical page number.
However, if reference is made to the address translation table each time an address translation is performed, the overhead for address translation will increase; therefore, considering the locality of address reference, it is generally practiced to cache the previously used address translations (mapping between virtual page number and physical page number) in high-speed memory. This memory is called the address translation buffer or translation look-aside buffer (TLB).
Previously, the TLB has been implemented mostly by a small-capacity associative memory. However, since the virtual address space is enlarging (for example, to a 64-bit space) to accommodate increasing program size, it is becoming common for microprocessors to integrate a large capacity TLB with high hit rate in order to. increase performance.
On the other hand, in the case of a large-capacity TLB, if associativity (the number of ways) is increased, not only the physical size of the memory but the access time also increases. Accordingly, associativity has to be kept low, and this limits the number of address translations that can be cached simultaneously for a main memory page having the same index address.
This limitation leads to a limitation on the TLB entry lock function, a performance enhancing technique generally applied to program and data regions having a high frequency of use and, in some cases, having to be resident in main storage for correct operations. That is, the TLB entry function is necessary to ensure that address translations for the code and data regions of an OS will remain cached in the TLB, but in the case of a low associativity TLB, the number of TLB entries capable of holding address translations to be locked is small (limited by the number of ways), and as it turned out, this can lead to the problem that proper system operation cannot be guaranteed.
In previous microprocessors, this problem was solved by increasing the associativity of the TLB, which was possible since the number of TLB entries was relatively small. However, with increasing performance of microprocessors, there has arisen the need to provide a larger number of TLB entries. In view of this, in recent microprocessors, not only to provide a large number of TLB entries but also to solve the above problem, it is beginning to be practiced to provide in addition to a large-capacity TLB a relatively small TLB for entry lock purposes. However, if more than one TLB is provided, when the OS performs replacement of TLB entries, it becomes necessary to select a TLB for entry storage by examining entry lock bits, and this leads to increased overhead.
In cases where hardware automatically performs replacement of TLB entries by searching through the address translation table in the main memory, one possible method is to divide the TLBs between one for holding locked entries and one for holding nonlocked entries, and to have the hardware automatically select the TLB for entry storage, and this in fact serves to reduce the overhead. However, when indexing into the TLBs for address translation, the plurality of TLBs have to be indexed into simultaneously and, when multiple memory accesses are to be performed simultaneously, the large-capacity TLB has to be provided with increased number of ports, resulting in the problem that the size further increases and the access time becomes longer.
SUMMARY OF THE INVENTION
The present invention has been devised in view of the above-outlined problems, and an object of the invention is to provide a microprocessor equipped with a large-capacity TLB and capable of avoiding the limitations imposed on the TLB entry lock function while reducing the overhead for address translation, and also to provide an address translation method for the microprocessor.
According to the present invention, there is provided a microprocessor for performing dynamic address translation from a virtual address to a physical.address on a page-by-page basis, the microprocessor comprising: (a) an address translation buffer having an entry lock function and including (1) a 2nd-level buffer organized as a lower hierarchy of the address translation buffer and having no entry lock function, and (2) a 1st-level buffer organized as a higher hierarchy of the address translation buffer and having the entry lock function, the 1st-level buffer having higher associativity than the associativity of the 2nd-level buffer; and (b) control logic for controlling operation of the address translation buffer.
Preferably, the 2nd-level buffer is larger in capacity than the 1st-level buffer.
Preferably, address translation for each page is stored in an address translation table residing in a main memory managed by an operating system, the address translation table has a data structure that contains a specifier indicating whether or not a corresponding address translation is to be locked in the address translation buffer, and the control logic locks an entry in the 1st-level buffer in accordance with the lock specifier contained in the data structure of the address translation table.
Preferably, the control logic selects an entry to be replaced in the address translation buffer in accordance with a prescribed replacement algorithm and notifies the operating system, and the operating system performs the replacement of the entry in the address translation buffer.
Preferably, when an entry replacement by the operating system occurs, if the address translation table a in the main memory shows that the address translation to be newly registered is specified to be locked, then the newly registered address translation is stored in the 1st-level buffer and held locked therein.
Preferably, when an entry replacement by the operating system occurs, if the address translation table in the main memory shows that the address translation to be newly registered is specified to be locked, then the newly registered address translation is stored in the 2nd-level buffer and, at the same time, is stored in the 1st-level buffer and held locked therein.
Preferably, when the control logic has selected in accordance with the replacement algorithm an entry in the 2nd-level buffer as the entry to be replaced, the control logic reports the selection of the entry in the 2nd-level buffer to the operating system, and the operating system accomplishes the replacement by only replacing the entry in the 2nd-level buffer, thereby maintaining intact the address translation locked in the 1st-level buffer.
Preferably, for entries other than the entry specified to be locked, a relationship always holds such that any entry stored in the 1st-level buffer is also stored in the 2nd-level buffer.
Preferably, the control logic selects an entry to be replaced in the address translation buffer in accordance with a prescribed replacement algorithm, retrieves the address translation to be newly registered from the address translation table residing in the main memory, and performs the replacement of the entry in the address translation buffer.
Preferably, when performing the replacement of the entry in the address translation buffer, the control logic refers to the address translation table in the main memory to see whether or not the address translation to be newly registered is sp
Butler Michael
Krishna Murali V.
Kubo Masahito
Parikh Vipul
Shen Gene
Dinh Ngoc
Fenwick & West LLP
Yoo Do Hyun
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