Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2000-01-21
2003-06-24
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S220000, C710S314000, C710S051000, C710S260000, C710S107000, C370S351000, C370S366000, C370S386000, C370S387000, C370S388000
Reexamination Certificate
active
06584528
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessors in which a plurality of resources use memories and memory devices therefor, and more specifically, to a microprocessor in which a plurality of resources share a single memory, and which permits no wait accesses in parallel.
2. Description of the Background Art
A microprocessor has a plurality of resources that access an internal memory, the resources including a data access control unit and a command fetch control unit. It is desired that these resources operate in parallel with one another, and thus, it is desirable that these resources are allowed to access the internal memory in parallel and with no wait.
Conventionally, such no wait access has been enabled by providing a memory dedicated for each internal resource. For example, a conventional microprocessor with Harvard architecture has a memory dedicated for data and a memory dedicated for commands, and these memories are allocated to the data access control unit and the command fetch control unit via a bus dedicated for data and a bus dedicated for commands, respectively. Thus, it is possible to perform command fetch and data access in parallel with no need of arbitration, which improves throughput of pipelined execution of instructions within a processor.
In such a conventional microprocessor, however, memory capacity dedicated for a corresponding resource is fixed. Therefore, different chips made of combinations of different memory capacities have been required for specific microprocessors with specific memory capacities required by specific applications.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a microprocessor which allows a plurality of resources to access a memory in parallel with no wait, and which is readily reconfigurable in accordance with a change in memory capacity, and a memory device therefor.
Another object of the present invention is to provide a microprocessor which allows a plurality of resources to access a shared memory in parallel with no wait, and which is readily reconfigurable in accordance with a change in memory capacity allocated to respective resources, and a memory device therefor.
A still another object of the present invention is to provide a microprocessor which allows a plurality of resources to access a memory in parallel with no wait, which is readily reconfigurable in accordance with a change in memory capacity, and which also is able to handle an illegal access to the memory without excessively increasing the amount of hardware, and a memory device therefor.
A further object of the present invention is to provide a microprocessor which allows a plurality of resources to access a shared memory in parallel with no wait, which is readily reconfigurable in accordance with a change in memory capacity allocated to respective resources, and which also is able to arbitrate memory access contention without excessively increasing the amount of hardware, and a memory device therefor.
A microprocessor according to the present invention includes: a first bus and a second bus capable of operating simultaneously; a single port memory divided into a plurality of banks; a bus switch circuit provided between the plurality of banks and the first and second buses; and a processor core connected to the first and second buses and the single port memory.
Each of the plurality of banks can be selectively coupled to the first and the second buses by the bus switch circuit. The banks can separately be allocated to the plurality of resources coupled to the first and second buses. Simply changing the number of banks to be allocated will alter the memory capacity allocated to each resource.
Preferably, the bus switch circuit includes a plurality of bus switches each provided between corresponding one of the plurality of banks and the first and second buses, and controlled by bus designating information given to the corresponding bank.
The bus switches can be controlled independent of activities on the first and second buses, by providing the bus switching circuit with the bus designating information. The bus designating information may be provided directly to the bus switch via an external pin, or may be written into a storage element temporarily and then provided via this storage element to the bus switch.
Each bank of the memory can be allocated to a resource independent of the activities on the buses. Therefore, when memory capacity to be allocated to each resource is known, it is possible to configure the microprocessor optimally in advance.
Each of the plurality of bus switches may further include an exception generating portion which detects occurrence of an access to a corresponding bank on a bus that is other than the bus coupled to the corresponding bank, generates an exception, and applies it to the processor core. If a resource generates an access to a bank that is not originally allocated thereto, the access must be handled as an illegal access. According to the present invention, the exception can be generated when such an access is detected, and is supplied to the processor core. Thus, it is possible to handle the illegal access by a program performed on the processor core, without having to add special hardware.
Each of the plurality of bus switches may include a selector circuit for dynamically selecting either the first bus or the second bus based on the activities thereon, to couple an input/output path of a corresponding bank to the selected bus.
This enables dynamic allocation of banks to respective resources based on the activities on the first and second buses, instead of allocating the banks to the resources in advance. Thus, it is possible to determine memory capacity to be allocated to each resource, not in a unit of a bank, but in a unit that is smaller than the bank.
The selector circuit may include an access request detecting portion that detects an access request on either the first bus or the second bus, and couples the bus with the access request to the input/output path of the corresponding bank. A bus is coupled to a designated bank only when an access request to the bank is actually generated on the bus. Thus, it is possible to flexibly reconfigure the microprocessor for applications in which banks cannot be allocated in advance.
The selector circuit may further include a simultaneous access detecting portion that detects occurrence of simultaneous access requests to a same bank on the first bus and the second bus, and generates an exception that will be applied to the processor core. When access requests to the same bank occur simultaneously, these contending requests must be arbitrated. In the microprocessor of the present invention, an exception is generated and supplied to the processor core. Thus, the access requests can be arbitrated by an exception handling program performed on the processor core. Therefore, it is possible to arbitrate access requests without having to add excessive hardware.
The memory device according to another aspect of the present invention is a memory device for use in a microprocessor having a processor core coupled to first and second buses, which includes a single port memory divided into a plurality of banks, and a bus switch circuit provided between the plurality of banks and the first and second buses.
The plurality of banks of the memory device can be selectively allocated to the first and second buses, and therefore, the respective banks can be allocated to resources connected to the first and second buses. The memory capacity to be allocated to each resource can readily be altered by changing the number of the banks to be allocated.
The method of operating the microprocessor according to a still another aspect of the present invention includes: the step of preparing bus designating information corresponding to the plurality of banks, and the step of operating a plurality of bus switches such that input/output paths of corresponding banks are selectively switched to the first bus or the second bus, according
Kurafuji Takashi
Yamada Akira
King Justin
Ray Gopal C.
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