Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2007-06-12
2007-06-12
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
10776266
ABSTRACT:
A translation lookaside buffer has a plurality of entries in which address translation information obtained by translating a virtual address into a physical address is registered. The entries each have a priority bit that is set when the registered address translation information is required to be resident. At the time an entry substitution request occurs while the priority bits of all the entries are in a set state, a control circuit for controlling the translation lookaside buffer chooses as a subject of substitution an entry that has been least recently referred to, irrespective of states of the priority bits. This allows execution of the entry substitution with the priority bits in all of the entries being set.
REFERENCES:
patent: 4373179 (1983-02-01), Katsumata
patent: 4463420 (1984-07-01), Fletcher
patent: 4682281 (1987-07-01), Woffinden et al.
patent: 4731739 (1988-03-01), Woffinden et al.
patent: 4797814 (1989-01-01), Brenza
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 5511178 (1996-04-01), Takeda et al.
patent: 5623619 (1997-04-01), Witt
patent: 5644748 (1997-07-01), Utsunomiya et al.
patent: 5737752 (1998-04-01), Hilditch
patent: 6292871 (2001-09-01), Fuente
patent: 6862663 (2005-03-01), Bateman
patent: 4-338848 (1992-11-01), None
Bataille Pierre
Schlie Paul
LandOfFree
Microprocessor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microprocessor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microprocessor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3875316