Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Reexamination Certificate
2002-05-03
2004-12-21
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
Reexamination Certificate
active
06834339
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a technique for reducing the power consumption of a microprocessor.
2. Related Background Art
Many microprocessors have several operating modes such as a normal mode, a slow mode, and a stand-by mode as functions thereof. In a mode such as the slow mode in which a low power consumption is assumed, it is likely that instructions to be executed are limited to relatively fewer kinds and are executed repeatedly. However, the circuit scales of programmable logic arrays (PLAs) that operate are unchanged even though only limited instructions are executed, which means that unnecessary power consumption occurs even in the slow mode.
The following will describe a conventional microprocessor.
FIG. 10
is a block diagram illustrating a schematic configuration of a common microprocessor.
100
is a CPU, which is connected with external circuits such as a ROM
500
, a RAM
600
, and a peripheral circuit
700
via buses. The CPU
100
includes an instruction decoder
400
, a data path
300
, and a bus interface
200
, so that data communication with the external circuit or within the CPU is carried out via the bus interface
200
.
Next, a common operation will be described. Data input from the ROM
500
are fed into the instruction decoder
400
via the bus interface
200
, and are divided into an instruction code and operand data by an instruction buffer
800
. The instruction code output from the instruction buffer
800
is fed into an instruction code conversion circuit
900
and is supplied as a microcode to the bus interface
200
, the data path
300
, and the instruction decoder
400
. Each block operates according to the microcode supplied thereto.
FIG. 11
is a block diagram illustrating a configuration of a conventional instruction code conversion circuit
900
.
It should be noted that in
FIG. 11
, T
1
and T
2
denote latch timings in accordance with a system clock clk for latching signals supplied to the respective blocks. T
1
is a falling edge of the system clock clk, and T
2
is a rising edge of the system clock clk.
The instruction code conversion circuit
900
is a circuit block for converting an instruction code taken out of ROM data into a microcode.
910
denotes a status register that latches a state signal as a part of the microcode at timings T
2
.
920
denotes an instruction register that latches the instruction code output from the instruction buffer
800
shown in
FIG. 10
at timings T
2
.
930
denotes a PLA that decodes an output signal from the instruction register
920
and the status register
910
.
940
denotes a microcode output control register that latches a decode signal output from the PLA
930
at timings T
1
and outputs a microcode.
The state signal and the instruction code are latched at timings T
2
by the status register
910
and the instruction register
920
, respectively, and are outputted to the PLA
930
. The PLA
930
decodes output signals of the instruction register
920
and the status register
910
, and outputs the decoded result as a decode signal. The microcode output control register
940
latches the decode signal at a timing T
1
of the next cycle, and outputs the same as a microcode.
However, in the foregoing conventional microprocessor, in the case where instructions limited in number are executed repeatedly, as in the slow mode, power is wasted since all the PLA circuits operate.
SUMMARY OF THE INVENTION
Therefore, the present invention is to solve the aforementioned problems, and it is an object of the present invention to provide a microprocessor whose power consumption is reduced optimally according to an execution instruction code and an operation mode.
To achieve the foregoing object, a microprocessor according to the present invention includes a first PLA, a second PLA, a selecting means, and a control means. The first PLA outputs a first PLA microcode based on an instruction code and a state signal. The second PLA outputs a second PLA microcode and a comparison determination signal based on the instruction code, the state signal, and a slow mode setting signal The selecting means selects either the first PLA microcode or the second PLA microcode according to the comparison determination signal, and outputs the selected one as a microcode. The control means activates one of the first and second PLAs and deactivates the other according to the comparison determination signal. In the foregoing microprocessor, the second PLA processes several instructions among all the instructions to be processed by the first PLA, and includes a first register, a second register, and a comparison control circuit. The first register stores instruction codes and state signals for the several instructions. The second register stores microcodes that correspond to the instruction codes and the state signals stored in the first register. The comparison control circuit compares data in the first register with the instruction codes and the state signals inputted in the slow mode according to the slow mode setting signal, and outputs the comparison result as the comparison determination signal. In the case where the comparison determination signal indicates a matching state, the second PLA outputs the microcode corresponding to the matched data of the first register from the second register as a second PLA microcode.
In other words, considering that in the slow mode, instructions are relatively limited and the limited instructions are executed repetitively, a second PLA dedicated for the execution of limited instructions is provided in addition to the first PLA for the normal operation. Further, instruction codes, state signals, and microcodes corresponding to the instruction codes and state signals can be set arbitrarily in the second PLA, and in the case where the instruction codes and the state signals to be executed in the slow mode match the data set in the second PLA, the operation of the first PLA is stopped, while the microprocessor is controlled according to a microcode outputted from the second PLA.
This reduces the power consumption in the slow mode.
Furthermore, the control means (control circuit) preferably causes the first PLA to stop a circuit operation by fixing input data to be supplied to the first PLA according to the comparison determination signal.
Furthermore, the first register and the second register preferably are composed of ROMs. This makes it unnecessary for an external ROM of the microprocessor to have a program region for initialization, thereby allowing the capacity of the external ROM to decrease, and reducing the period of time for the initialization.
Furthermore, the control means (power source control circuit) preferably stops the power supply to the first PLA by switching the power supply to the first PLA or the second PLA according to the comparison determination signal. This prevents the generation of OFF leak current, thereby allowing the power consumption in the slow mode to be reduced further.
Furthermore, data in the first register (C register) preferably are rewritable at all times according to data in the instruction register and the status register, and data in the second register (D register) preferably are rewritable at all times according to the microcode. With this, by changing the values set into the first register and the second register dynamically, the power consumption can be reduced optimally according to an execution frequency of an instruction, irrespective of an operational mode.
Furthermore, it is preferable that frequently-executed instructions are extracted from a ROM source file, converted into ROM codes, and arranged in the second PLA. This allows the low power consumption to be achieved, and at the same time, even if the program development is carried out outside a microprocessor manufacturer, there is no need to disclose detailed information concerning performance and architecture of the microprocessor such as instruction codes, state data, and microcodes, thereby making it possible to maintai
Asada Hiroaki
Kondo Shuji
Okabe Yoji
Coleman Eric
Merchant & Gould P.C.
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