Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2002-05-28
2004-07-06
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Reexamination Certificate
active
06759309
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the formation of vertical electrical interconnects within multiple layers of substrates, wherein a portion of the substrate layers are glass and a portion of the substrate layers are single-crystal silicon. Layers of other materials may be present as well. The invention is particularly advantageous in the fabrication of microcolumns, and especially an array of microcolumns of the kind used in electron optics, including electron microscopes and lithography apparatus.
BACKGROUND OF THE INVENTION
As the size requirements for various electromechanical devices continue to diminish, there has been substantial interest in the manufacture of micro-electromechanical structures (MEMS). A typical MEMS structure incorporates at least one electrical device in combination with one or more mechanical device. Various attempts have been made to produce MEMS structures using common semiconductor processing techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and plasma etching. However, a typical MEMS structure is considerably larger than a typical semiconductor structure. The layers of materials used in a typical MEMS structure tend to be much thicker and cover a greater surface area than those used in conventional semiconductor devices. Therefore, depositing a layer of material using a CVD or PVD technique, or etching a material layer using plasma etching, can be too slow, such that the amount of time required to manufacture a MEMS structure using these techniques is prohibitive.
Many MEMS structures utilize various electronic devices etched out of silicon wafers. These electronic devices are then electrically isolated from each other by a layer of dielectric material. Recent work has focused on the use of glass sheets in lieu of dielectric layers which have been deposited using conventional semiconductor deposition techniques (which, as discussed above, are typically too slow to be practical for use in the deposition of dielectric layers of sufficient thickness for MEMS applications). Stacks of alternating layers of glass and conductive material (such as silicon) can be bonded together to produce various MEMS structures.
Anodic bonding has been one of the techniques used to bond the conductive layer to the glass layer. In some instances, a semiconductor material such as silicon is used as the conductive layer, and the glass layer is a borosilicate glass, such as PYREX® or BOROFLOAT® (Schott Glass Technologies, New York, N.Y.). In the alternative, the glass layer may be a lithium aluminosilicate-&bgr;-quartz glass-ceramic, such as Prototype PS-100, available from HOYA Co., Tokyo, Japan. The advantage of this latter glass is that anodic bonding may be performed at a temperature of about 180° C.
In order for the MEMS structure to function as a whole, it may be advantageous to form vertical electrical interconnects between the various conductive layers which have been electrically isolated from one another by sheets of glass. Because the interconnect is sealed within a multilayered sandwich and is difficult (if not impossible) to repair, it is important to obtain a robustness of these interconnects which is higher than wire bonding. A robust interconnect can be used in a harsh environment. To produce vertical electrical interconnects between conductive or semiconductive layers in a multilayered structure, there are a number of different possibilities, some of which are summarized below.
U.S. Pat. No. 4,525,766, issued Jun. 25, 1985, to Kurt E. Petersen, discloses a hermetically sealed electrical feedthrough conductor formed across the periphery or boundary between a hermetically sealed region on a semiconductor substrate and a second or external region thereof. A planar insulative layer is formed on the surface of the semiconductor (silicon) substrate along the predetermined path of the feedthrough conductor across the periphery of the insulative layer. The insulative layer has at least one planar projection on each side thereof which extends out to a point. Subsequently, a planar metal feedthrough conductor layer is applied which substantially covers the insulative layer, including planar projections. An insulator element sized to encapsulate the region to be sealed is then mallory bonded (anionic bonded) to the periphery, including the feedthrough conductor. The planar projections are said to form a compression bond that eliminates any tenting region that would otherwise form beneath the insulator element at the edges of the feedthrough conductor and the underlying insulative layer. The electrical feedthrough connections formed in this manner are generally in the same horizontal plane as the surface of the semiconductor substrate on which they are formed.
U.S. Pat. No. 5,584,956, issued Dec. 17, 1996, to Lumpp et al., describes a method for producing feedthroughs in a substrate having a front surface and a back surface. A sheet of material is bonded to the substrate using an adhesive. A laser is then used to form a hole through the substrate, where the laser radiation has a given wavelength at a power sufficient to ablate a hole through the substrate and a portion of the sheet behind the substrate, thereby creating a feedthrough in the substrate. The sheet of material may be conductive or an insulator. If the sheet is conductive, the sheet may remain bonded to the substrate to serve as a ground plane for the substrate. If the sheet is an insulator, the feedthrough is an insulated feedthrough, and if the sheet is conductive, the feedthrough is a conductive feedthrough. The procedure can be extended to produce a two-conductor feedthrough, where a wire is inserted, as illustrated in
FIG. 6
d
, to produce a structure useful as a coaxial cable.
U.S. Pat. No. 5,656,553, issued Aug. 12, 1997, to Leas et al., illustrates a prior art approach to the problem of fabricating microcolumns of chips. As in other prior art, the assembly and subsequent contacting of the ICs in the stack is done after dicing of the chip or chip arrays out of the silicon wafers. In addition, the conductive interconnections disclosed can be said to be “three dimensional” only in the rather limited sense that “side surface metallization” is applied to the peripheral edges of planar arrays of integrated chips subsequent to the dicing of the wafer.
In an article by R. De Reus et al. in Microelectronics Reliability (Vol. 38, pp. 1251-1260 (1998)), entitled “Reliability of Industrial Packaging For Microsystems”, the authors discuss packaging concepts for silicon-based micromachine sensors exposed to harsh environments. Various protective coatings of specialized materials, glue types, and thin-film anodic silicon-to-silicon wafer bonding processes are described. Through-hole electrical feedthroughs with a minimum line width of 20 &mgr;m and a density of 250 wires per centimeter were obtained by applying electro-depositable photoresist. Hermetically sealed feedthroughs were obtained using glass frits, where the seal is said to withstand pressures of 4000 bar.
U.S. Pat. No. 5,998,292, issued Dec. 7, 1999, to Black et al., describes a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about 1 millimeter or less. Specifically, the method comprises etching at least one hole, defined by walls, at least partly through a semiconductor material; forming a layer of electrically insulating material to cover the walls; and forming an electrically conductive material on the walls within the channel of the hole. The micro-post wiring may be used in devices of the kind described in the patent.
In an article by Xiaghua Li et al. entitled “High density electrical feedthrough fabricated by deep reactive ion etching of Pyrex glass” (Technical Digest, MEMS 2001, from the 14
th
IEEE International Conference on Micro Electro Mechanical Systems, pp. 98-101 (Jan 2001)), the authors describe a fabrication technology for producing PYREX® glass (manufactured by Corning Glass of Corning, N.Y.) with a fine pitc
Applied Materials Inc.
Church Shirley L.
Cuneo Kamand
Geyer Scott B.
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