Microelectronic devices having interconnects with planarized spu

Details Microelectronic devices having interconnects with planarized spu Microelectronic devices having interconnects with planarized spu

1997-09-15

2000-06-06

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

257496, 257635, 257750, 257752, H01L 3100, H01L 2358, H01L 2348, H01L 2352

Patent

active

060722258

ABSTRACT:
An interconnect in a microelectronic device is formed by forming a first mesa on a substrate. A first insulation layer is then formed on the substrate, the first insulation layer covering the first mesa to define a step at an edge thereof. A second mesa is formed on the first insulation layer adjacent the step, the second mesa being lower than the step. A second insulation layer is formed on the substrate, covering the second mesa and forming a step in the second insulation layer overlying the step in the first insulation layer. A spun-on-glass (SOG) layer on the second insulation layer, and then is planarized to expose a first portion of the second insulation layer at the step in the second insulation layer and to expose a second portion of the second insulation layer overlying the second mesa, thereby defining a planarized SOG region between the step and the second mesa. A third insulation layer is formed on the substrate, covering the planarized SOG region, and portions of the second and third insulation layers overlying the second mesa are then removed to expose a portion of the second mesa. An interconnecting region is formed on the second insulation layer which extends through the second and third insulation layers to contact the exposed portion of the second mesa. Microelectronic devices so formed are also discussed.

REFERENCES:
patent: 5384483 (1995-01-01), Huang
patent: 5465003 (1995-11-01), Lur et al.
patent: 5777258 (1998-07-01), Yajima

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