Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-01-30
2003-12-23
Jean, Frantz B. (Department: 2155)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S058000, C710S062000, C710S072000, C710S073000, C710S074000, C711S211000, C711S212000
Reexamination Certificate
active
06668301
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits. More specifically, the present invention relates to microcontrollers that are capable of interfacing with an external device, such as memory devices and multi-functional peripheral devices.
Over the years, various microcontrollers have been developed for various applications. Presently, many microcontrollers are designed to interface with a single type of external memory device, such as a particular type of SRAM or DRAM or a multi-functional peripheral. Additionally, microcontrollers are typically designed to interface with a specific subtype of external device (e.g., different SRAM subtypes having different interface requirements). By way of example, a microcontroller typically includes capabilities for interfacing with either an SRAM configured to receive separate read and write enable signals, an SRAM configured to receive a combined read and write enable signal, or an SRAM configured to receive a read enable signal and more than one write enable signal.
FIG. 1A
is a diagrammatic representation of an external device
100
of a first subtype (Type I) and associated I/O pins. Motorola's MCM6323, 64K×16 Bit, 3.3 V, Asynchronous Fast Static RAM is an example of a Type I external device, a specification of which is included in Appendix A as Item 1 (incorporated herein by reference in its entirety). As shown, the Type I external device
100
is configured to receive a plurality of address (ADR) signals, a plurality of data signals (DB), a chip select (CS!) signal, a read (RD!) enable signal, a write (WR!) enable signal, a byte enable low (BEL!) signal, and a byte enable high (BEH!) signal. (An “
49
” denotes that the signal is enabled at a low state). The BEL! and BEH! are optional, and some Type I external devices do not include such inputs.
These signals that are received by the external device
100
provide many functions that are required for accessing memory within the external device
100
. The CS! signal is required to enable and initiate access to the external device
100
. The RD! signal is needed to enable and initiate a read from the external device
100
, and the WR! signal is needed to enable and initiate a write to the external device
100
. When a RD! signal is provided to the external device that indicates a read operation is to be performed, the external device
100
outputs data onto the DB. Specifically, the data is output from a memory location within the external device
100
that is specified by the received ADR signals. Conversely, when a WR! is provided that indicates a write operation is to be performed, the external device
100
receives data via the DB into the specified memory location. The BEL! and BEH! are optional, and some Type I external devices do not include such inputs. Additionally, some Type I external devices include more than one pair of byte enable signals.
FIG. 1B
are typical timing diagrams for I/O signals that are required as input into the Type I external device
100
of
FIG. 1A
to enable a read operation. As shown, the timing diagrams include a plurality of address (ADR) signals, a chip select (CS!) signal, a read (RD!) enable signal, a write (WR!) enable signal, a byte enable low (BEL!) signal, and a byte enable high (BEH!) signal. As shown, the ADR signals transition from a first value
102
to a second value
106
during period
104
. The CS! signal transitions from a high value
108
to a low value
112
during a portion of the second ADR value. When the CS! signal is at a low value, access to the external device
100
is enabled. After the external device
100
is enabled, the RD! signal transitions from a high value
114
to a low value
118
to enable a read operation. The WR! signal remains at a high value
120
such that a write operation is not enabled.
Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state
122
to a low state
124
to enable the read operation only for certain bytes of data. For example, if the BEL signal remains high and the BEH signal transitions to a low value, data is read only from an upper byte of the specified memory location and not from the lower byte. That is, only the output drivers of the enabled bytes are activated within the external device
100
.
FIG. 1C
are typical timing diagrams for I/O signals that are required as input into the external device
100
of
FIG. 1A
to enable a write operation. As shown, the I/O signals for a write operation are similar to the I/O signals for a read operation. However, the WR! signals transitions from a high value
166
to a low value
170
to enable the write operation, and the RD! signal remains at a high state
164
.
Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state
172
to a low state
176
to enable the write operation only for certain bytes of data. For example, if the BEL signal remains high and the BEH signal transitions to a low value, data is written only into an upper byte of the specified memory location and not into the lower byte.
FIG. 2A
is a diagrammatic representation of an external device
200
of a second subtype (Type II) and associated I/O pins. Motorolla's MC68HC901 Multi-Function Peripheral is an example of a Type II external device, a specification of which is included in Appendix A as Item 2 (incorporated herein by reference in its entirety). As shown, Type II is configured to receive a plurality of address (ADR) signals, a plurality of data signals (DB), a chip select (CS!) signal, a combined read and write (RD/WR!) enable signal, a byte enable low (BEL!) signal, and a byte enable high (BEH!) signal.
The BEL! and BEH! are merely illustrative, and some external devices may have a different number of byte enable inputs. For example, some external devices (e.g., a 32 bit external device) require more than one pair of byte enable signals, while other external devices (e.g., an 8 bit external device) only require a single byte enable (or data enable) signal.
The Type II device has different read and write mechanisms than the Type I external device. The Type II device requires a combined read and write enable (RD/WR!) signal, while the Type I device requires separate read and write enable (RD! and WR!) signals.
FIG. 2B
are typical timing diagrams for I/O signals that are required as input into the external device of
FIG. 2A
to enable a read operation. As shown, the CS! signal transitions from a high state
208
to a low state
212
to enable access to the Type II external device. Additionally, the RD/WR! signal remains at a high value
214
to enable the read operation. Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state
216
to a low state
218
to enable the read operation only for the indicated bytes(s).
FIG. 2C
are typical timing diagrams for I/O signals that are required as input into the external device of
FIG. 2A
to enable a write operation. As shown, the I/O signals for a write operation are similar to the I/O signals for a read operation. However, the RD/WR! transitions from a high state
264
to a low state
267
to enable a write operation. Additionally, one or both of the byte enable signals (e.g., BEL and BEH) may also transition from a high state
266
to a low state
270
to enable the write operation only for the indicated bytes(s).
FIG. 3A
is a diagrammatic representation of an external device
300
of a third subtype (Type III) and associated I/O pins. Cypress' CYM1838, 128K×32 Static RAM Module is an example of a Type III external device, a specification of which is included in Appendix A as Item 3 (incorporated herein by reference in its entirety). As shown, Type III is configured to receive a plurality of address (ADR) signals, a
Fish & Richards n P.C.
Infineon Technologies North America Corp.
Jean Frantz B.
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