Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-09-13
2005-09-13
Beausoliel, Robert (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S031000, C712S227000, C703S028000
Reexamination Certificate
active
06944794
ABSTRACT:
The invention is the microcontroller, which comprises CPU, a bus controller, an instruction address bus of a first bit number and an instruction code bus of a second bit number, which connect between the CPU and bus controller, and, further, a debug support unit, which is connected to the instruction address bus and instruction code bus. This debug support unit is also connected to an external in-circuit emulator via a tool bus of a third bit number that is smaller than the first bit number and via a bus-status signal line that reports on the status of this tool bus. The debug support unit has a data output circuit, which, in response to the status information signal, when the branch information contains a branch, outputs the converted instruction address serially to the tool bus, and when the branch information contains no branch, outputs a branchless signal to the tool bus.
REFERENCES:
patent: 5053949 (1991-10-01), Allison et al.
patent: 5491793 (1996-02-01), Somasundaram et al.
patent: 6233673 (2001-05-01), Higashida
patent: 6430682 (2002-08-01), Dwyer, III
patent: 6493833 (2002-12-01), Utsumi
Okabayashi Toru
Tagawa Koutarou
Beausoliel Robert
Matthew Aaron D.
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