Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-06-03
2003-04-01
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S104000, C713S002000
Reexamination Certificate
active
06542955
ABSTRACT:
The present invention relates generally to microcontrollers and, particularly, to the use and management of on-chip non-volatile memory.
BACKGROUND OF THE INVENTION
Traditionally, microcontrollers that are compatible with the industry standard 8051 architecture assume a memory organized into four address spaces, each with corresponding physical memory circuits. The four address spaces correspond to: internal program code, internal data, external program code and external data. In this context, “internal” means code or data that is stored in controller on-chip memory and “external” means code or data that is stored in off-chip memory. An illustration of the conventional 8051 memory organization is shown in FIG.
1
.
Referring to
FIG. 1
, the internal program memory
102
is typically implemented as mask-ROM
120
or other non-volatile memory, the internal data memory
106
as 128 or 256 bytes of SRAM plus a special function register (SFR) array
140
, and the external program and data memories
104
,
108
each as up to 64K bytes of SRAM 110, 112. The internal data can be read and written by internal programs or external programs via an internal memory bus. The internal program code, which is read-only, can be fetched over the same internal bus. The external program code, which is read-only, can be fetched over an external bus. The external data can be read and written by external programs or internal programs via the same external bus.
Each area of memory is accessed in response to particular instructions. For example, internal program code is fetched via the internal data bus one byte at a time in response to a move ode (MOVC) instruction, and no other instruction, issued by an internal or external program. The MOVC instruction has two different formats:
Format
Description
MOVC @
move onto the internal bus a byte of the program code
(A + DPTR)
from the internal program memory at the address given
by the sum of the Accumulator part of the MOVC
instruction (A) and the contents of the data pointer
DPTR, which is a 16-bit value.
MOVC @
move a byte of the program code from the internal
(A + PC)
program memory at the address given by the sum of the
Accumulator A and the contents of the program counter
register PC, which is a 16-bit value.
Internal and external program code reads are differentiated by the location of the fetched code byte. CPU will detect whether the code is in internal or external program memory and fetch the code accordingly.
Internal data is fetched and written via the internal bus using a wide range of memory access instructions issued by an internal or external program in one of four addressing modes:
Address Mode
Description
Register Mode
Data is stored in one of the registers R0-R7 in the
selected register bank (4 register banks each with 8
registers).
Direct Mode
Data is stored in either an SFR or a location in the lower
128 bytes of the internal SRAM.
Indirect Mode
Data is stored in a location in the 256 bytes of the
internal SRAM. The address is stored in a register.
Indexed Mode
Data is stored in a location addressed by the sum of a
base register (program counter PC or Data Pointer
DPTR) and the Accummulator as the index register.
External Program code is fetched via the external bus in response to a move code (MOVC) instruction issued by an internal or external program. The MOVC instruction has two different formats:
Format
Description
MOVC @
move a byte of the program code from the external data
(A + DPTR)
memory at the address given by the sum of the
Accumulator A and the contents of the register DPTR,
which is a 16-bit value.
MOVC @
move a byte of the program code from the external data
(A + PC)
memory at the address given by the sum of the address
A and the contents of the program counter register PC,
which is a 16-bit value.
The external data is fetched and written via the external data bus in response to a move external (MOVX) instruction issued by an external or internal program. The MOVX instruction has 16-bit and 8-bit formats:
Format
Description
MOVX @ DPTR
move the data from the external data memory at the
address given by the contents of the 16-bit register
DPTR.
MOVX @ Ri
move the data from the external data memory at the
address given in the 8-bit register Ri (i=0 or 1) of the
selected register bank.
For additional information on the MCS-51 family of controllers, please see the publication, “MCS®-51 Microcontrollers Family User's Manual (published by Intel, February, 1994) p. 1-1 to p. 2-75.
Given this architecture, traditional 8051 microcontrollers cannot be used in applications where it is necessary to retain internal data in the absence of a power-supply. This problem has been addressed in the Atmel C
51
family of microcontrollers (i.e., the 89S8252 and 89LS8252), which is now described with reference to FIG.
2
. Additional information on memory organization and programming in the Atmel C
51
family of microcontrollers is provided in the following documents, which are incorporated herein by reference:
(1) “AT89S8252 Primer,” Atmel Application Note, Rev. 1018A-03/98; and
(2) “8-Bit Microcontroller with 8K Bytes Flash, AT89S8252,” pp. 4-105 to 4-135, Atmel AT89-series Microcontroller Databook, Rev. 0401D-A-12/97.
Referring to
FIG. 2
, the Atmel C51 family of microcontrollers implements the 8051 memory organization of
FIG. 1
using four separate memory circuits 162-168, but uses non-volatile Flash memory
170
for the internal program code memory and non-volatile EEPROM
174
and SRAM
180
for the internal data memory. This arrangement ensures that the internal data can be maintained in the absence of power and can be reprogrammed.
Access to all but the internal data is the same as in the traditional 8051 memory scheme. The internal data SRAM
180
can be accessed using the same range of memory access instructions and access modes described above (register, direct, indirect). Additionally, Atmel allows the internal EEPROM
174
to be accessed through the MOVX instruction which, in the traditional 8051 architecture, is used to access only the external data memory
168
. In the Atmel scheme, access to the internal EEPROM
174
via the MOVX instruction is enabled when an EEMEN bit in the special function register (SFR)
190
is set. When the EEMEN bit is cleared, the MOVX instruction accesses the external data memory
168
.
The Atmel memory scheme provides non-volatile memory for internal data in a manner that is consistent with the traditional 8051 memory organization scheme and memory access instructions. However, due to the Flash (program) and EEPROM (data) memories
170
,
174
being physically distinct, the situation could arise where there is not enough room for internal data storage in the EEPROM
174
even though there is room in the Flash memory
170
(and vice-versa for internal program code storage). As a result, this scheme does not make efficient use of the relatively expensive, on-chip non-volatile memory
170
,
174
. Also, while data can be stored in the internal program Flash memory, the usefulness of such data is limited as it would be read-only during program execution. Once the data in the program area is programmed it cannot be altered until the whole program is reprogrammed.
Additionally, it is difficult to reprogram the Flash memory
170
to update the programs or data stored therein. This is because the Flash memory
170
can only be reprogrammed on block basis, i.e., updating any byte in the Flash memory requires erasing the entire block first. Among other things, this prevents the Flash memory
170
from being programmed by software executing on the microcontroller or by external devices through the microcontroller's serial port. Additionally, it would not be practical to program a Flash memory in this byte-by-byte fashion.
Therefore, there is a need for an 805 1-compatible microcontroller that provides on-chip, non-volatile memory for internal data and program code storage in such a manner that all on-chip, non-volatile memory is eff
Anderson Matthew D.
Kim Matthew
MacPherson Kwok & Chen & Heid LLP
Programmable Microelectronics Corporation
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