Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-08-07
2004-06-01
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S167000, C710S027000, C710S058000, C365S230020
Reexamination Certificate
active
06745301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to eight bit microcontrollers, and particularly to executing memory access cycles by a microcontroller in a page mode of operation.
2. Description of the Related Art
An 8-bit microcontroller is used extensively in products today because of its small size, low power consumption, and flexibility. Because the market for 8-bit microcontrollers continues to grow, silicon manufacturers are pushing the development of faster, more efficient 8-bit microcontrollers.
The 8051 microcontroller is a heavily used microcontroller at the present time. It is a very powerful and easy to program integrated circuit. Numerous software and hardware products are available for use with 8051 microcontrollers. A wide range of support tools and third-party products are also available to support 8051 microcontrollers, including emulators, compilers, prototyping/programming adapters, and development systems. In addition, many different variants of 8051 microcontrollers are available to satisfy the requirements posed by various applications.
High-speed 8051 microcontrollers are a family of 8051-compatible microcontrollers providing increased performance compared to the traditional 8051 family of controllers. High-speed 8051 micros are 100% instruction set and object code compatible with the instruction set utilized by the traditional 8051 microcontrollers.
To make faster 8051 microcontrollers, designers have implemented more efficient code, faster clocks, and faster circuits to handle the faster speeds. These faster implementations have resulted in internal memory cycles (i.e., memory cycles which retrieve information from memory within the 8051 microcontroller) being substantially reduced and in many instances requiring only a single machine/clock cycle to execute. In addition, the access times of memory devices external to 8051 microcontrollers have been markedly reduced over the years. Despite the improvement in performance time within the 8051 microcontroller and within external memory, however, external memory cycles (i.e., memory cycles which retrieve information from memory external to 8051 microcontrollers) in the faster 8051 microcontrollers have not improved to the same extent.
For instance, a traditional 8051 microcontroller accesses external memory by using a first parallel input/output (I/O) port to communicate the low byte address multiplexed with data and a second parallel I/O port to communicate the high byte address. An 8051 microcontroller manufactured by Intel® utilizes a first parallel I/O port for communicating the low byte address and a second parallel I/O port for communicating the high byte address multiplexed with data. Because data communicated in an external memory cycle can be in either direction, the I/O port handling the data must be tristated or undriven for a predetermined period of time before data can be placed on the I/O port. Consequently, the bus structures for parallel I/O ports in existing 8051 microcontrollers inherently provide an additional delay not necessarily related to the internal operation of the existing 8051 microcontrollers and external memory.
Based upon the foregoing, there is a need for an 8051 microcontroller that more effectively executes external memory cycles.
SUMMARY OF THE INVENTION
Embodiments of the present invention overcome above-identified shortcomings in prior 8051 microcontrollers and satisfy a significant need for an 8051 compatible controller having enhanced capabilities in accessing external memory. In an exemplary embodiment of the present invention, a microcontroller includes first input/output (I/O) port dedicated as a data port and a second I/O port dedicated as an address port during memory cycles in a page mode of operation. The memory address for a memory cycle is a multiplexed address. By separating data from address in memory cycles when in a page mode, the microcontroller is capable of executing page mode memory cycles faster than prior 8051 microcontrollers.
In another exemplary embodiment of the present invention, the microcontroller selectively configures the first and second I/O ports in one of a plurality of bus structures for performing memory cycles in a page mode of operation. In one configuration, the first I/O port is a dedicated data port and the second I/O port is dedicated as an address port, as described above. In another configuration, the first and second I/O ports may be dedicated to handling data and addresses for memory cycles according to a bus structure of existing microcontrollers. In the first configuration, the cycle time of the memory cycles may be selected from a plurality of different cycle times to accommodate both high speed and lower speed external memory devices.
REFERENCES:
patent: 5253214 (1993-10-01), Herrmann
patent: 5652847 (1997-07-01), Padwekar
patent: 6021453 (2000-02-01), Klingman
patent: 6327192 (2001-12-01), Lee
patent: 6477625 (2002-11-01), Pascucci et al.
Gorski Joseph P.
Ma Edward Tangkwai
Dallas Semiconductor
Jenkens & Gilchrist
Padmanabhan Mano
Vital Pierre M.
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