Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-11-14
2006-11-14
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S027000, C714S055000
Reexamination Certificate
active
07137036
ABSTRACT:
A microcontroller including a CPU (Central Processor Unit) is capable of detecting the error of its structural part. The CPU executes a first initialization phase in response to a power-on reset signal output from a power-on reset circuit, then executes a second initialization phase in response to a start signal, and then executes usual processing. The CPU outputs a single timer run signal during first initialization phase and repeatedly outputs the timer run signals during usual processing. A watchdog timer starts timing in response to the timer run signal and then outputs an overflow signal on the elapse of a preselected period of time. After receiving the power-on reset signal from the power-on reset circuit, an error detector feeds the CPU with the start signal in response to an overflow signal output from the watchdog timer for the first time.
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Baderman Scott
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Schell Joseph
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