Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1998-03-12
2001-01-16
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C711S163000, C711S150000, C358S296000, C370S351000, C710S020000
Reexamination Certificate
active
06175881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a microcontroller suitable for a multitask process for receiving data from an external device during an arithmetic operation of the CPU (central processing unit) using data from a memory device.
2. Prior Art
Multitasking is well known as a method of improving the computing speed of a computer. In a computer performing a multitask process, for example, a write operation of data from the external device to another location of the main memory takes place simultaneously with the arithmetic process of the CPU (central processing unit) using a part of the main memory.
The control of a multitask operation can be achieved either by software or hardware. In the control by software, however, the main memory region is taken up by a control program, so that hardware control is often adopted to meet the requirement of more effective use of the memory.
The techniques for executing multitasking by hardware have been revealed by literature as follows.
Literature (1) JP-A-5-274154, Program Load Method and Memory Back-up Method
Literature (2) JP-A-7-210449, Dual Port RAM Access Circuit
Literature (3) JP-A-3-105440, Shared Memory Access Method The literature (1) discloses a case where a dual port RAM for the main memory is divided in its application. Specifically, the serial memory portion of the RAM is dedicated to DMA (direct memory access) and the random access memory portion is dedicated to the CPU.
The literature (2) discloses a structure that while the CPU accesses the first memory region of the dual port RAM, the data processing circuit can access the second memory region.
The literature (3) discloses a structure that a free memory bank can be used as a memory region accessible by another processor.
Meanwhile, the prior-art techniques mentioned above have the following problem. In those methods that use the dual port RAM in a subdivided form as indicated in literatures (1) and (2), it is necessary to control a plurality of subdivisions of the dual port RAM, so that the peripheral circuits have to be in complicated configurations. Therefore, those methods are not suitable for forming a less expensive microcontroller in a less expensive configuration.
The method using memory banks as indicated in literature (3) lacks in operational facility because data must be input or output to and from the memory by using another processor.
SUMMARY OF THE INVENTION
To solve the above problem, the present invention adopts the following arrangement.
<Arrangement 1>
According to the present invention, there is provided a microcontroller having a memory connected to the CPU through a data bus and an address bus, comprising:
a memory for a multitask process separate from the above-mentioned memory;
data bus switching means for switching, by control of the CPU, the connection of the multitask-process memory either to the above-mentioned data bus or a data bus leading to an external device;
address bus switching means for switching, by control of the CPU, the connection of the multitask-process memory either to the address bus or to an address bus for the external device; and
address supply means for generating and supplying address signals used to store data sent from the external device in the multitask-process memory connected both to the data bus of the external device and the address bus data.
<Arrangement 2>
In the microcontroller according to the present invention, the address supply means, connected with a clock oscillator to output a clock signal at a frequency same as the operation clock frequency of the external device, supplies an address signal in synchronism with the external device.
REFERENCES:
patent: 4827406 (1989-05-01), Bischoff et al.
patent: 4953930 (1990-09-01), Ramsey et al.
patent: 5276799 (1994-01-01), Rivshin
patent: 5490279 (1996-02-01), Golbert et al.
patent: 5799207 (1998-08-01), Wang et al.
patent: 5864692 (1999-01-01), Faraboschi et al.
patent: 7-210449 (1985-05-01), None
patent: 3-105440 (1991-05-01), None
patent: 5-274154 (1993-10-01), None
Lee Thomas C.
OKI Electric Industry Co., Ltd.
Vuong Thu-Huong
Wenderoth , Lind & Ponack, L.L.P.
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