Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1995-03-03
2001-06-05
Hua, Ly V. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S055000
Reexamination Certificate
active
06243837
ABSTRACT:
BACKGROUND OF THE INVENTION
The microcomputer according to the invention is based on a microcomputer of the generic type of the main claim. Data Sheet MC 68 F 333 TS/D, Motorola 1992, already discloses a microcomputer which has, apart from the central processing unit, a programmable, non-volatile memory (flash EEPROM), input/output components, a monitoring circuit (watchdog timer), and also a volatile memory (code RAM), into which there can be written program data which can be accessed by the instruction counter of the central processing unit. All the said components are integrated on a chip. The microcomputer is configured such that it can both access program data which are located in the programmable, non-volatile memory and can execute a program which is located in the volatile memory. In both cases, the monitoring circuit is activated, ie. it must be ensured that, in the case of regular program flow, the monitoring circuit is reset at the correct time, since otherwise the monitoring circuit carries out a resetting of the microcomputer. A disadvantage of this microcomputer is that haphazard changes of the memory content in the volatile memory (for example due to interfering EMC radiation) can cause the forming a situation in which the monitoring circuit is reset at the correct time although the program flow is irregular.
SUMMARY OF THE INVENTION
The microcomputer according to the invention having the characterizing features of the main claim has in comparison the advantage that in it there is a separation between execution of a program in the programmable, non-volatile memory (ROM mode) and execution of a program in the volatile memory (RAM mode). The separation is constituted by the fact that resetting of the monitoring circuit is not possible at all in the second operating state (RAM mode). A resetting of the monitoring circuit can take place only in the first operating state (ROM mode). The forming of an EMC radiation-induced program loop in which resetting of the monitoring circuit at the correct time occurs in spite of a disturbed program flow is in this way made more difficult.
It is advantageous on the one hand that the selection of the at least two different operating states of the microcomputer takes place implicitly by a decoding of the address space. As a result, the programming effort is kept low. On the other hand, it is advantageous if the selection of the at least two different operating states takes place by an explicit switching-over of operating modes of the microcomputer. This achieves a more pronounced separation of the two operating states, so that a programmer can keep a better check on the operating states.
Furthermore, it is particularly advantageous that the microcomputer includes a program flow counter. This counter is activated at least whenever the microcomputer is operating in the second operating state (RAM mode). The program flow counter, which in the case of regular program flow is respectively set in a defined way after a certain number of program instructions, makes an additional check on the program flow possible.
It is furthermore advantageous that there are included in the microcomputer means which check the reading of the program flow counter and suppress the emission of monitoring signals if the checking of the program flow counter indicates an irregular program flow. This virtually rules out the forming of an EMC interference-induced program loop in which monitoring signals are emitted at the correct time in spite of irregular program flow.
For simple checking of the reading of the program flow counter, it is advantageous that the microcomputer has a reference counter, which is incremented before each checking of the reading of the program flow counter, that it has means which compare the current counter reading of the program flow counter with the current counter reading of the reference counter and that it detects an irregular program flow if the counter readings of program flow counter and reference counter do not match.
For a simple way of realizing a suppression of monitoring signals it is advisable to provide in the microcomputer a configuration register in which, if there is a change of operating state (from ROM mode to RAM mode), a flag in the configuration register is set, whereby an electronic device is switched in such a way that it blocks the line for the transmission of monitoring signals.
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patent: 5068783 (1991-11-01), Tanagawa et al.
patent: 5119381 (1992-06-01), Yamamoto
patent: 5408645 (1995-04-01), Ikeda et al.
patent: 5521880 (1996-05-01), McClure
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patent: 5-274216 (1993-10-01), None
Motorola Semiconductor Technical Data, 1992, MC 68 F333, pp. 3-7, 28-30, 100-102 and 110.
Grote Walter
Zimmermann Jurgen
Hua Ly V.
Robert & Bosch GmbH
Striker Michael J.
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