Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-09-07
2004-04-27
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S017000, C714S030000, C714S047300, C717S127000, C702S064000
Reexamination Certificate
active
06728900
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a microcomputer and to a method of testing such a microcomputer.
From U.S. Pat. No. 5,802,071 it is known to test a microcomputer by executing a test program from a test program memory. As described in this document, the test program memory makes it possible to test the microcomputer independent of the content of the application program. This document also describes how to test items in the microcomputer by observing the results produced by executing instructions from the program.
The document does not discuss testing timing of instruction execution. In particular it does not describe testing whether the microcomputer can execute instructions fast enough. However, in a conventional synchronous microcomputer slow execution of an instruction will show itself automatically in the form of erroneous results produced by execution of that instruction.
This will not work in asynchronous microcomputers. Asynchronous microcomputers are microcomputers that receive successive instructions by means of handshaking, completion of one instruction triggering delivery of the next instruction. If an asynchronous computer executes instructions too slowly, the instructions will produce the right results, but execution will take too much time. In contrast, a synchronous computer uses a periodic clock to trigger execution of successive instructions. Consequently, if the synchronous computer executes instructions too slowly, instructions will be executed in time, but the results will be wrong, which can be easily detected.
The instruction execution speed of an instruction by an asynchronous computer can be measured by measuring the time needed to execute that instruction a number of times. However, the result of this measurement may not be an accurate measure of the time needed to execute that instruction. The measured execution time may also involve delays due to instruction fetch delays and the time needed for program control flow instructions. If the instruction is executed by executing copies of the instruction in successive locations in instruction memory, instruction testing moreover will take considerable time or memory space, because all the copies need to be loaded or stored in memory.
U.S. Pat. No. 5,802,071 also does not discuss measurement of current consumed by the computer during instruction execution. For low power applications it may be necessary to guarantee that current consumption of a manufactured computer, in particular a computer on a chip like a microcontroller, will be below a specified level. To guarantee this, the current consumed during execution of particular instructions must be measured. For an accurate measurement, the measurement should be free from variable current consumption factors due to fetching or execution of flow control instructions.
SUMMARY OF THE INVENTION
It is an object of the invention to provide for measurement of the speed of execution of an instruction by a microcomputer without inaccuracy due to time needed for program flow control.
It is a further object of the invention to provide for measurement of the speed of execution of an instruction by a microcomputer without requiring much time or memory space for the loading the instruction.
It is another object of the invention to provide for measurement of the current consumption during execution of an instruction by a microcomputer without inaccuracy due to current consumption needed for program flow control.
The microcomputer according to the invention is described in claim 1. According to the invention the microcomputer is capable of operating in a test mode in which normal instruction sequencing is suppressed in order to enforce cyclical application of the same instruction from the same source to an instruction execution unit. In this way, significant timing variations due to other effects than execution of the instruction are eliminated. In an asynchronous microcomputer it is advantageous to arrange the computer according to the invention. In this way, the time needed to execute the instruction can be accurately measured during testing. Of course, the invention can also be applied to a synchronous microcomputer, for example to detect any spread in execution speed that may not show up as errors in the result of the instructions.
In an embodiment, the computer comprises a special test instruction memory, outside an address space used during normal program execution. During test, the instruction is read repeatedly from the test instruction memory. By placing a specific instruction in the test instruction memory and switching the microcomputer into the test mode, it can be measured accurately whether the parts of the microcomputer involved in the execution of that instruction are sufficiently fast, because delays caused by addressing or reading the normal memory are eliminated. Preferably, the test instruction memory contains only one instruction, the microcomputer re-feeding that instruction to the instruction execution unit each time when its previous execution has been completed. Thus, a minimal amount of memory is needed for executing the instruction and execution is highly reproducible. In case the instruction consists of multiple words that are loaded sequentially, the microcomputer preferably loads the words sequentially and returns to the first word once the execution of the instruction has been completed. In this case, the test instruction memory needs to contain only as many words as the longest possible single instruction of the microcomputer.
Preferably, the microcomputer is incorporated in an integrated circuit with a scan-test interface, for serially inputting and outputting test information via a shift register. In this case, an instruction is preferably loaded via the shift register, together with a command that causes the microcomputer to execute the loaded instruction repeatedly in test mode in order to test the time needed for executing the instruction.
A method of testing that uses such a microcomputer comprises loading an instruction into a test memory location and executing that instruction repeatedly. Preferably, the method comprises loading several instructions in turn and repeatedly executing each instruction before loading the next instruction. With different instructions the speed of different parts of the microcomputer can be tested.
REFERENCES:
patent: 4870345 (1989-09-01), Tomioka et al.
patent: 4870573 (1989-09-01), Kawata et al.
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5706294 (1998-01-01), Takahashi et al.
patent: 5802071 (1998-09-01), Fang et al.
patent: 6106572 (2000-08-01), Halpern
patent: 6539498 (2003-03-01), Sato
Beausoliel Robert
Koninklijke Philips Electronics , N.V.
Puente Emerson
Waxcer Aaron
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