Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-08-16
2003-11-11
Myers, Paul R. (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S324000, C713S320000, C710S262000
Reexamination Certificate
active
06647503
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer, and more particularly relates to a microcomputer which is capable of loading a program into a DRAM or an SRAM memory installed therein and executing the thus loaded program.
2. Description of the Related Art
In recent years, a non-volatile memory such as a mask ROM, an EPROM, a flash memory and the like is provided for storing a program data in a microcomputer, for the purpose of facilitating the development or modification of a program and so on. On the other hand, a vast-storage DRAM is installed in a microcomputer which is used for processing a large amount of data at a high speed. When developing a program for the development of a new product related to a microcomputer carrying a DRAM therein, efficiency of the development is assured by checking the operation of a microcomputer after transmitting a program data from outside the microcomputer chip to the on-board DRAM. Once the development of a program is completed, the program data whose operation has already been checked is stored in a non-volatile memory; namely a mask ROM which is stored almost permanently in the microcomputer, a flash memory which is provided outside the microcomputer chip and so forth.
In order to secure the stable operation of a microcomputer, it is quite important to operate the microcomputer by the same procedure with the one used for executing the operation test. For this reason, in the microcomputer carrying a DRAM therein, it is arranged such that a program data is first transmitted from the non-volatile memory to the DRAM when powered ON, and as soon as the reset state is released thereafter, the CPU accesses the program data thus stored in the DRAM, so that the same operation under exactly the same procedure as the one employed for developing the program can be executed.
For maintaining the data in the DRAM installed in the microcomputer, it is necessary to execute a periodical potential charge; which is so-called a refreshing operation, and for this reason, clock signals must be supplied to a circuit in: which the refreshing operation is carried out. It is to be noted that the most efficient method for saving power consumption of a microcomputer is to suspend the operation of a clock signal generating circuit. However, if the operation of the clock signal generating circuit is suspended, the refreshing operation cannot be properly carried but, and subsequently the data stored in the DRAM is destroyed. Due to this, another clock signal generating circuit, namely a clock signal generating circuit exclusively used for the DRAM should be provided in the DRAM control circuit for executing the refreshing operation.
Since the conventional microcomputer carrying a DRAM therein is configured as such, in order to secure the stable operation of the microcomputer, two clock signal generating circuits are required within one microcomputer chip; namely a clock signal generating circuit for a system clock and that exclusively used for the DRAM, so that the function and the grade of integration of the microcomputer, whose ultimate purpose is to implement maximum functions within a limited chip area, are thereby degraded.
In addition, the fact that a clock signal generating circuit exclusively used for the DRAM is required for securing the stable operation of the microcomputer increases the total power consumption.
Still further, there is also another problem that when the CPU is put in a runaway state, an erroneous writing is likely to occur to the program data area within the DRAM, so that even when the runaway state is recovered thereafter, the microcomputer cannot operate properly due to the destruction of the program data. The same phenomenon can be observed even in the case where an SRAM is used as the program memory instead of the DRAM.
SUMMARY OF THE INVENTION
The present invention has been proposed to solve the problems aforementioned, and it is an object of the present invention to provide a microcomputer carrying a DRAM therein as a program memory, which requires only one clock generating circuit and is thus capable of greatly reducing the power consumption.
It is also another object of the present invention to provide a microcomputer carrying a DRAM or an SRAM therein as a program memory, which can properly operate even in the case where the CPU is put in a runaway state and thereafter the program runaway is recovered.
The microcomputer according to a first aspect of the present invention is constructed in such a manner that it comprises: a CPU, a DRAM installed within the microcomputer, a non-volatile memory storing a program data therein, which non-volatile memory being installed in the microcomputer or provided outside the microcomputer, an interface commonly used among various circuits within the microcomputer, a system clock generating circuit, which generates clock signals and is also. , capable of suspending and regenerating the clock signals, respectively in response to a system clock stop signal and a system clock generation signal, a peripheral circuit which is capable of outputting an interrupt signal requesting the system clock generation to the CPU, and a control circuit which re-transmits the program data from the non-volatile memory to the DRAM in response to a re-initialize request signal output from the CPU, and also outputs an access prohibition signal for prohibiting the access to the data stored in the DRAM and an access prohibition release signal for releasing the prohibition of access.
The microcomputer according to further aspect of the present invention is constructed in such a manner that it comprises; a CPU, a DRAM installed within the microcomputer, a non-volatile memory storing a program data therein, which non-volatile memory being installed in the microcomputer or provided outside the microcomputer, an interface commonly used among various circuits within the microcomputer, a system clock generating circuit for generating clock signals, a peripheral circuit which is capable of detecting the runaway of the CPU and also outputting an interrupt signal requesting the recovery from the runaway to the CPU, and a control circuit which re-transmits the program data from the non-volatile memory to the DRAM in response to a re-initialize request signal output from the CPU, and also outputs an access prohibition signal for prohibiting an access to the data stored in the DRAM and an access prohibition release signal for releasing the prohibition of access.
The microcomputer according to further aspect of the present invention is constructed in such a manner that it comprises; a CPU, an SRAM installed within the microcomputers a non-volatile memory storing a program data therein, which non-volatile memory being installed in the microcomputer or provided outside the microcomputer, an interface commonly used among various circuits within the microcomputer, a system clock generating circuit for generating clock signals, a peripheral circuit which is capable of detecting the runaway of the CPU and also outputting an interrupt signal requesting the recovery from the runaway to the CPU, and a control circuit which re-transmits the program data from the non-volatile memory to the SRAM in response to a re-initialize request signal output from the CPU, and also outputs an access prohibition signal for prohibiting an access to the data stored in the DRAM and an access prohibition release signal for releasing the prohibition of access.
REFERENCES:
patent: 4631701 (1986-12-01), Kappeler et al.
patent: 5283885 (1994-02-01), Hollerbauer
patent: 5410707 (1995-04-01), Bell
patent: 5890195 (1999-03-01), Rao
patent: 5903507 (1999-05-01), Arimoto
patent: 5928365 (1999-07-01), Yoshida
patent: 6097658 (2000-08-01), Satoh et al.
patent: 6216233 (2001-04-01), Baweja
patent: 6243768 (2001-06-01), Khandekar
patent: 6338108 (2002-01-01), Motomura
patent: 6412052 (2002-06-01), Keeth et al.
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Myers Paul R.
Phan Raymond N
LandOfFree
Microcomputer with re-initialization of DRAM or SRAM using... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microcomputer with re-initialization of DRAM or SRAM using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer with re-initialization of DRAM or SRAM using... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3120231