Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1997-10-20
2001-07-31
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
Reexamination Certificate
active
06269429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer incorporating an electrically erasable programmable flash memory.
2. Description of the Prior Art
The first prior art of a microcomputer which can write/erasure data in/from a flash memory is disclosed in Japanese Unexamined Patent Publication No. 5-266219. In this prior art, a microcomputer having the first mode for controlling the flash PROM using a CPU and the second mode for controlling the flash PROM using a circuit outside the semiconductor circuit is described.
FIG. 1
is a block diagram of such a conventional microcomputer incorporating a flash memory and allowing write and erase processing. The microcomputer comprises a central processing unit
1
, a flash PROM
2
, a register
3
, a RAM
4
, an interrupt request generation unit
5
, a timer unit
6
, an internal bus
7
, and a ROM
8
.
The central processing unit (to be referred to as a CPU hereinafter)
1
comprises a program counter (to be referred to as a PC hereinafter)
11
for writing data transferred via the internal bus
7
and outputting an address signal ADR to the flash PROM
2
, an instruction register
12
for latching an instruction code transferred via the internal bus
7
, an instruction decoder
13
for decoding the instruction code from the output from the instruction register
12
, an execution control unit
14
for executing the instruction in accordance with the decoded result from the instruction decoder
13
, an ALU
15
for loading, e.g., two data transferred via the internal bus
7
, performing calculation in accordance with the execution control unit
14
, outputting the calculation result to the internal bus
7
, and outputting the flag change according to the calculation result to a program status word (to be referred to as PSW hereinafter) register
16
constituted as a register, and an interrupt request reception unit
17
for controlling interrupt processing in accordance with an interrupt request signal IRQ output from the interrupt request generation unit
5
.
The flash PROM
2
comprises a flash memory (memory cell)
21
, a write/erase/read control circuit (to be referred to as a WER circuit hereinafter)
22
, a data latch
23
for latching, from the internal bus
7
, data to be written in the flash memory
21
, a command register
24
for latching, from the internal bus
7
, a command to be supplied to the WER circuit
22
, an address latch
25
for latching, from the internal bus
7
, an address to be used in the write mode to the flash memory
21
, and a selector
26
for switching the address signal ADR and the output signal from the address latch
25
and outputting the selected signal to the flash memory
21
as an address. When the command register
24
is in an NOP mode representing processing other than write/erase processing, i.e., normal read processing, the selector
26
outputs the address signal ADR to the flash memory
21
as an address. When the command register
24
is not in the NOP mode, the selector
26
outputs the output signal from the address latch
25
to the flash memory
21
as an address.
The RAM
4
receives an address from the internal bus
7
and receives/outputs data from/to the internal bus
7
. The timer unit
6
is constituted by a timer for performing a count operation in synchronism with an internal clock, and a compare register. When the value of the timer coincides with that of the compare register, the timer unit
6
outputs an interrupt signal to the interrupt request generation unit
5
and clears the timer. The interrupt request generation unit
5
receives an interrupt request from a peripheral circuit such as the timer unit
6
and outputs the interrupt request signal IRQ to the interrupt request reception unit
17
of the CPU
1
. The ROM
8
stores a program for writing data in the flash PROM
2
and is used in writing data in the flash PROM
2
.
The operation of the microcomputer having the above arrangement will be described.
[Execution of Instruction]
Execution of a program will be described. The PC
11
outputs, as the address signal ADR, an address at which an instruction to be executed is stored. Since the command register
24
is set in the NOP mode, the selector
26
outputs the address signal ADR to the flash memory
21
. The flash memory
21
outputs the content to the internal bus
7
through the WER circuit
22
in accordance with the address. The instruction code output to the internal bus
7
is latched by the instruction register
12
and decoded by the instruction decoder
13
. The execution control unit
14
designates the operation of the ALU
15
and designates a register in accordance with the decoded result from the instruction decoder
13
. The calculation result from the ALU
15
is transferred via the internal bus
7
and written in the register
3
. The flag of the PSW register
16
changes in accordance with the calculation result from the ALU
15
. The PC
11
is incremented by one after execution of the instruction to prepare an address at which an instruction to be executed next. Instructions are executed in the above way.
[Flash PROM Write Processing Based on Interrupt Processing]
Flash PROM write processing using the flow of interrupt processing will be described next. To write 1-byte data in the flash PROM
2
, a time of about 10 &mgr;s is required. On the other hand, the microcomputer operates at a high speed in accordance with an operation clock of, e.g., 20 MHz. For this reason, after the command register of the flash PROM
2
is set in a write mode, processing must wait until write processing is enabled. The wait time is controlled using the timer unit
6
. When an interrupt signal is output from a peripheral circuit such as the timer unit
6
to the interrupt request generation unit
5
, the interrupt request generation unit
5
determines the interrupt priority. If reception of the interrupt is enabled, the interrupt request signal IRQ is set at “1”. When the interrupt request signal IRQ is set at “1”, execution of the program is stopped, and interrupt processing is started. The interrupt request reception unit
17
stores the contents of the PC
11
and the PSW register
16
in the RAM
4
on the basis of a control signal from the execution control unit
14
and thereafter sets, in the PC
11
, a start address necessary for the interrupt processing program. With this setting, the interrupt processing program is started. When the interrupt processing program is ended, the contents stored in the RAM
4
are returned to the PC
11
and the PSW register
16
, thereby recovering the state before the interrupt processing.
FIG. 2A
shows an example of a program for writing 1-byte data at address
1000
H of the flash PROM
2
. A
0
to A
6
on the left side represent addresses of the memory at which the program is stored. This program is stored in the ROM
8
and used in writing data in the flash memory.
A
0
: Set address
1000
H in the address latch
25
A
1
: Set data DATA
0
to be written first in the data latch
23
A
2
: Set the command register
24
in the write mode
A
3
: Set the compare register of the timer unit
6
at a value for satisfying the write time of the flash memory
21
and start the count operation of the timer
A
4
: Set a HALT mode
In the HALT mode, the CPU stops while a peripheral circuit such as the timer unit
6
operates.
FIG. 2B
shows an interrupt processing program.
IA
0
: Set the command register
24
in the NOP mode
IA
1
: Stop the count operation of the timer unit
6
IA
2
: Return
FIG. 3
is an operation timing chart showing changes in the PC
11
, the address latch
25
, the data latch
23
, the command register
24
, and the like. When the command register
24
is set in the write (WR) mode, the selector
26
outputs, as an address, the value “1000H” set in the address latch
25
to the flash memory
21
. When the HALT mode is set, the CPU
1
stops, PC
11
stops while keeping the address A
4
indicated, and the access to the flash PROM
2
is ended. Wh
Ellis Kevin L.
McGuireWoods LLP
NEC Corporation
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