Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-04-19
2004-02-03
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S726000, C714S727000, C717S124000
Reexamination Certificate
active
06687857
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer that can be debugged while it is in practical use.
2. Description of the Prior Art
Referring next to
FIG. 14
, it illustrates a block diagram showing the structure of a prior art microcomputer as disclosed, as a first conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. In the figure, reference numeral
1
denotes a user target system, such as a microcomputer-equipped appliance, and numeral
2
denotes a host computer. The user target system
1
includes a serial interface
3
connected to the host computer
2
, a memory
4
, a monitor program
5
stored in the memory
4
, an I/O
6
, a microprocessor
7
, a register built in the microprocessor
7
, and a processor bus
9
.
When debugging the user target system
1
, the host computer
2
is connected to the serial interface
3
. The microcomputer
7
can execute the monitor program
5
to access the memory
4
, the I/O
6
, and the register
8
by the processor bus
9
. The microcomputer
7
can execute and control a user program using a software break instruction and then furnish execution results to the host computer
2
by way of the serial interface
3
.
Referring next to
FIG. 15
, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as a second conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. In the figure, reference numeral
11
denotes a debugging tool. A microprocessor
7
includes a register
12
, a sequencer
13
, a bus controller
14
, and a transmission path
15
. The other structure of the microcomputer of
FIG. 15
is the same as that of the microcomputer of FIG.
14
.
When debugging the user target system
1
, the debugging tool
11
and host computer
2
are connected to the serial interface
3
. The debugging tool
11
converts a command from the host computer
2
into an equivalent command intended for debugging, which can be understood by the sequencer
13
of the microprocessor
7
. The sequencer
13
of the microprocessor
7
can suspend the execution of a user program according to the command intended for debugging, and access the register
12
by way of the transmission path
15
and the memory
4
or I/O
6
using the bus controller
14
. The sequencer
13
of the microprocessor
7
can furnish execution results to the debugging tool
11
by way of the serial interface
3
. The debugging tool
11
can convert the execution results into equivalent data which can be understood by the host computer
2
and then furnish the data to the host computer
2
.
Referring next to
FIG. 16
, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as a third conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. A debugging tool
11
as shown in the figure includes a microprocessor
21
intended for debugging, a monitor program memory
22
, and a trace memory
23
. The other structure of the microcomputer of
FIG. 16
is the same as that of the microcomputer of FIG.
14
.
In general, the debugging system as shown in
FIG. 16
is called in-circuit emulator. When debugging the user target system
1
, the microprocessor
7
is removed from the user target system
1
. As an alternative, the microprocessor
7
is disabled. A probe of the debugging tool
11
can be connected to the part of the bus
9
to which the microprocessor
7
was connected, so that the debugging microprocessor
21
can alternatively operate. The debugging microprocessor
21
can execute a monitor program stored in the monitor program memory
22
built in the debugging tool
11
to control execution of a user program or access the memory
4
or I/O
6
. The debugging microprocessor
21
can execute a program stored in the memory
4
built in the user target system
1
as if the microprocessor
7
does. The debugging tool
11
includes the trace memory
23
to trace the status of the processor bus of debugging microprocessor
21
. The debugging microprocessor
21
can furnish trace information that cannot be obtained from the microprocessor
7
. Part of the internal state of the debugging microprocessor
21
, which cannot be traced via the processor bus
9
, can be traced.
Referring next to
FIG. 17
, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as a fourth conventional example, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. In the figure, reference numeral
31
denotes a logic analyzer connected to a user target system
1
. The other structure of the microcomputer of
FIG. 17
is the same as that of the microcomputer of FIG.
14
.
In general, the debugging system as shown in
FIG. 17
is called pre-processors. When debugging the user target system
1
, a probe of the logic analyzer
31
is connected to a processor bus
9
built in the user target system
1
, so that accesses to a memory
4
and an I/O
6
by a microprocessor
7
can be traced.
Referring next to
FIG. 18
, it illustrates a block diagram showing the structure of another prior art microcomputer as disclosed, as an embodiment, in Japanese Patent Application Publication (TOKKAIHEI) No. 8-185336, for example. A debugging tool
11
as shown in the figure includes a monitor program
41
. A user target system
1
includes an external debugging interface
42
. A microprocessor
7
includes a processor core
43
, a debugging module
44
, an internal debugging interface
45
, and an internal processor bus
46
. The other structure of the debugging system of
FIG. 18
is the same as that of the debugging system of FIG.
14
.
When debugging the user target system
1
, the debugging tool
11
is connected to the external debugging interface
42
of the user target system. The processor core
43
can execute the monitor program
41
stored in the debugging tool
11
by way of the internal debugging interface
45
and the debugging module
44
. At that time, the processor core
43
furnishes an address and size information to the debugging tool
11
. The debugging tool
11
then furnishes a corresponding code of the monitor program
41
to the core processor
43
. The monitor program
41
can implement execution control functions, such as reading and writing of a memory
4
or an I/O
6
, setting of hardware break points, and specifying of the starting address at which the execution of the user program is to be started. The debugging module
44
can implement a serial monitor bus function, which is enabled in debugging mode, and a PC trace function, a trace trigger function, a hardware break function, a software break function, a debugging interruption function, a debugging reset function, and a mask function, which are enabled in normal mode.
A problem with the prior art debugging system as shown in
FIG. 14
is that the monitor program
5
used for debugging a user program has to be pre-stored in the memory
4
of the user target system
1
and this results in upsizing of the memory
4
. A further problem is that when the memory
4
storing the user program to be debugged becomes unstable, the monitor program
5
for debugging the user program becomes unstable, too, thus being unable to debug the user program with reliability.
A problem with the prior art debugging system as shown in
FIG. 15
is that the transmission path
15
and the bus controller
14
intended for debugging have to be provided in order to access the register
12
, and this results in upsizing of the debugging system and hence an increase in the area of the chip.
A problem with the prior art debugging system as shown in
FIG. 16
is that since the connection between the user target system
1
and the debugging tool
11
is established by a probe, the connection by the probe easily becomes unstable and the user target system
1
therefore becomes unstable. Another problem is that a variety
Fukuzawa Fumitaka
Iwata Shunichi
Nasu Takashi
Beausoliel Robert
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Puente Emerson
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