Microcomputer timing control circuit provided with internal...

Details Microcomputer timing control circuit provided with internal... Microcomputer timing control circuit provided with internal...

2000-08-07

2003-10-07

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C327S143000, C327S012000, C326S016000

Reexamination Certificate

active

06631467

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer with an internal reset signal generator preferably applied to a superhighway automatic toll system, and particularly to an improved microcomputer that can effectively prevent runaway of internal circuits of the microcomputer due to variations in the timing of an external reset signal at power-up.
2. Description of Related Art
FIG. 5
is a block diagram showing a configuration of a conventional microcomputer. In
FIG. 5
, the reference numeral
25
designates a microcomputer;
26
designates a chip ground input terminal;
27
designates a chip higher potential power supply input terminal;
28
designates a chip reset input terminal; reference numerals
29
designate a pair of chip serial input/output terminals;
30
designate a pair of chip oscillator connection input/output terminals; and reference numeral
31
designates a chip port input/output terminal.
The reference numeral
32
designates an oscillator;
33
designates a clock generator;
34
designates a central processing unit;
35
designates a data bus;
36
designates a RAM (Random Access Memory);
37
designates a ROM (Read Only Memory);
38
designates a timer;
39
designates a serial communication circuit; and
40
designates a port circuit, all of which are internal circuits constituting the microcomputer.
Next, the operation of the conventional microcomputer will be described.
As shown in
FIG. 6
, a high-level external reset signal is supplied to the chip reset input terminal
28
after a predetermined time has elapsed from power on, which will reset the internal circuits
34
-
39
like the central processing unit. Subsequently, the reset of the internal circuits
34
-
39
like the central processing unit is released so that the central processing unit
34
achieves desired functions in accordance with programs stored in the ROM
37
.
With the foregoing configuration, the conventional microcomputer has a problem in that the internal circuits
34
-
39
can run away if the external reset signal is at the high level at the power-up as shown in
FIG. 7
, or if the external reset signal is driven to the high level on the power-up as shown in FIG.
8
. This is because the central processing unit
34
can start in such cases to execute a program from an address other than the address of a reset vector.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a microcomputer with an internal reset signal generator for effectively preventing runaway of internal circuits due to variations in the timing of the external reset signal at the power-up.
According to a first aspect of the present invention, there is provided a microcomputer with an internal reset signal generator for generating an internal reset signal from an external reset signal supplied to a chip reset input terminal and for supplying the internal reset signal to internal circuits of the microcomputer through a reset signal line, the internal reset signal generator comprising: a first two-input logic circuit having its first gate input terminal connected to the chip reset input terminal, for outputting a first logic signal at a low level only when its two gate input terminals are placed at a high level; an inverter for inverting the first logic signal and supplying its output to a second gate input terminal of the first two-input logic circuit; a capacitor connected between the second gate input terminal and a higher potential power supply terminal; and a second two-input logic circuit supplied with the first logic signal and the external reset signal, for changing the level of the internal reset signal only when both the inputs are at the high level.
Here, the internal reset signal generator may further comprise an inverter connected to an output of the second two-input logic circuit.
The first two-input logic circuit and the second two-input logic circuit may each consist of a two-input NAND circuit.
According to a second aspect of the present invention, there is provided an internal reset signal generator which generates an internal reset signal from an external reset signal supplied to a chip reset input terminal, the internal reset signal generator comprising: a first two-input logic circuit having its first gate input terminal connected to the chip reset input terminal, for outputting a first logic signal at a low level only when its two gate input terminals are placed at a high level; an inverter for inverting the first logic signal and supplying its output to a second gate input terminal of the first two-input logic circuit; a capacitor connected between the second gate input terminal and a higher potential power supply terminal; and a second two-input logic circuit supplied with the first logic signal and the external reset signal, for changing the level of the internal reset signal only when both the inputs are at the high level.
Here, the internal reset signal generator may further comprise an inverter connected to an output of the second two-input logic circuit.
The first two-input logic circuit and the second two-input logic circuit may each consist of a two-input NAND circuit.


REFERENCES:
patent: 4716521 (1987-12-01), Nagae
patent: 5157270 (1992-10-01), Sakai
patent: 5576650 (1996-11-01), Hirotani et al.
patent: 5767694 (1998-06-01), Ogata
patent: 5774649 (1998-06-01), Goh
patent: 5936443 (1999-08-01), Yasuda et al.
patent: 6417704 (2002-07-01), Nakajima et al.
patent: 0689290 (1995-06-01), None
patent: 355053761 (1980-04-01), None
patent: 358178430 (1983-10-01), None
patent: 60-19220 (1985-01-01), None
patent: 362003574 (1987-01-01), None
patent: 402096246 (1990-04-01), None
Vigyan Singhal et al., “The Case for Retiming with Explicit Reset Circuitry”, IEEE 1996, pp 618-625.

Affiliated with

Also associated with

Rating

Microcomputer timing control circuit provided with internal... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Microcomputer timing control circuit provided with internal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer timing control circuit provided with internal... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3111277