Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-10-15
1999-05-18
Pan, Daniel H.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39518306, 711 2, 36518905, G06F9/22;12/06
Patent
active
059059079
ABSTRACT:
A data reading testing method of a microcomputer loaded with a PROM being conducted under a normal operation mode. Setting the operation mode of the microcomputer to a ROM-less mode. Setting the externally extended function under the ROM-less mode. Diverging addresses to an externally extended region. Setting the microcomputer to the normal operation mode, upon which a CPU is to fetch instructions being previously provided to applicable addresses of the externally extended region, and to read the data from the PROM. Reading the data from the PROM. Evaluating the read data and terminating the reading test.
REFERENCES:
patent: 5307464 (1994-04-01), Akao et al.
patent: 5632024 (1997-05-01), Yajima et al.
patent: 5754764 (1998-05-01), Davis et al.
NEC Corporation
Pan Daniel H.
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