Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2000-03-01
2003-03-11
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S103000, C711S219000
Reexamination Certificate
active
06532529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer including an electrically programmable erasable non-volatile memory. More specifically, the present invention relates to a microcomputer including a flash memory which allows modification/overwriting of a program stored therein in a simple manner.
2. Description of the Background Art
Recently, as personal computers have come to be widely used, various and many peripheral devices of the personal computers have also come to be used widely. Such personal devices include CD-ROM (Compact-Disk Read-Only Memory) drives, DVD-ROM (Digital Video Disk Read-Only Memory) drives and hard disk drives. These peripheral devices have characteristically short development cycles. Specifications are improved one after another and control programs are improved in a very short period of time, and therefore control programs of these devices are frequently revised. For this reason, a microcomputer including a flash memory allowing modification/overwriting of a program in a simple manner is advantageous, and hence used dominantly.
In a flash memory of such a microcomputer, a program and data including device parameters, country code and a program version number are stored. When a program is revised, or when it becomes necessary to adapt states of the device to the conditions and terms under which the device is to be used, the data are overwritten.
Referring to
FIG. 1
, a conventional microcomputer including a flash memory includes a flash memory
3
storing data such as program, connected to a data bus
7
, an address bus
8
and read/write (RD/WR) signal line
9
. The microcomputer further includes a CPU (Central Processing Unit)
1
connected to data bus
7
, address bus
8
and RD/WR signal line
9
through a BIU (Bus Interface Unit)
2
for executing a program stored in flash memory
3
, an external bus I/F (interface) circuit
15
, an RAM (Random Access Memory)
4
, peripheral devices such as a timer and a serial I/O (Input/Output), and an interrupt controlling circuit
14
, which are all connected to data bus
7
, address bus
8
and RD/WR signal line
9
.
The microcomputer further includes an address predecoder
505
decoding an upper bit of an address applied through address bus
8
for selecting any of flash memory
3
, RAM
4
, peripheral device
13
and interrupt controlling circuit
14
and applying area signals ROMar, RAMar and SFRar (Special Function Register area), respectively.
Referring to
FIG. 2
, address predecoder
505
includes a predecoder
21
for the peripheral device
13
, an RAM predecoder
22
, and an ROM predecoder
23
. Predecoder
21
for the peripheral device, RAM predecoder
22
and ROM predecoder
23
are all connected to address bus
8
for receiving and decoding an upper address and outputting the signals SFRar, RAMar and ROMar, respectively.
CPU
1
is capable of overwriting contents of flash memory
3
. An operation mode of the microcomputer performing this process will be referred to as “flash memory overwriting mode.”
Generally, CPU
1
successively reads a program written in flash memory
3
and executes the program. In the flash memory overwriting mode, however, CPU
1
cannot read data written in flash memory
3
. This is because the control voltages and the states of circuit connection for performing erasure and writing of data in flash memory
3
are different in operation modes (generally referred to as “normal mode ” here) other than the flash memory overwriting mode.
Therefore, in the flash memory overwriting mode, operation is controlled such that an overwrite control program is transferred in advance from flash memory
3
to RAM
4
, and CPU
1
reads and executes the overwrite control program from RAM
4
.
Referring to
FIG. 3
, the controlling structure of the program executed by the CPU in the flash memory overwriting mode is as follows. When activated, the process transfers the flash memory overwrite control program which has been stored in flash memory
3
to RAM
4
(step S
110
; hereinafter, “step” is not repeated). Thereafter, control jumps to that area of the RAM to which the flash memory overwrite control program has been transferred (S
112
). In order to successively read and execute the program on RAM
4
, the overwriting mode of the flash memory is set (S
114
) and in S
116
, the flash memory is overwritten. When overwriting of the flash memory ends, the overwriting mode of the flash memory is terminated (S
118
).
In this manner, the contents of the flash memory are overwritten in the overwriting mode of the flash memory.
As can be seen from
FIG. 1
, the microcomputer includes an interrupt controlling circuit
14
. When there is an interrupt request from the peripheral device
13
such a timer or a serial I/O or from a terminal input, not shown, interrupt controlling circuit
14
interrupts execution of the process program by CPU
1
and executes an interruption process. In the interruption process, CPU
1
jumps to that address which is designated by a value stored in an address referred to as “interrupt vector” existing in flash memory
3
, and executes a program at that address, so that a process corresponding to the cause of interruption takes place.
More specifically, when there is an interruption, interrupt controlling circuit
14
automatically outputs an address of the interrupt vector to address bus
8
. CPU
1
receives this address, and reads an area designated by the address in flash memory
3
, that is, the value of the interrupt vector. Then, CPU
1
jumps to the address designated by the value. The above described series of processes are performed.
The interrupt vector area is generally in flash memory
3
from the following reason. Generally, information which must be held permanently such as the program and the interrupt vector is stored in flash memory
3
. If the interrupt vector area were placed in RAM
4
, it would become necessary to transfer the data of the interrupt vector to RAM
4
from flash memory
3
immediately after every activation of the microcomputer, as RAM
4
is volatile. In that case, however, interruption is not available if there is an interruption request in a period after reset termination until completion of data transfer of the interrupt vector to the RAM. Therefore, the interrupt vector is generally placed in flash memory
3
.
These results in the following problem in the flash memory overwriting mode. Assume that an interruption request is issued while a process in the flash memory overwriting mode described above is being performed by executing the program stored in RAM
4
. Here, CPU
1
always tries to read the interrupt vector of flash memory
3
. Flash memory
3
, however, is being overwritten, and therefore the result of such reading cannot be guaranteed.
In order to avoid such a problem, an interruption is inhibited while the flash memory is being overwritten, by the specification of the microcomputer. More specifically, when such an interruption occurs, the operation is not guaranteed, or alternatively, a mechanism is provided to prevent occurrence of an interruption, by hardware, in the flash memory overwriting mode.
As described above, in a microcomputer including a flash memory of the prior art, interruption is not available while the flash memory is under the overwriting operation. In recent equipments using microcomputers, a process referred to as background operation (BGO) is frequently performed. The BGO function refers to overwriting of data in a certain block within a flash memory while performing normal processing. The function is necessary for overwriting telephone books of cellular phones, overwriting of operational modes, channels, set temperature and other ambient conditions of home use and civil equipments, for example. If the interruption process is not available as in the microcomputer including a flash memory of the prior art, such BGO function cannot be attained.
A possible approach for this problem may be to include two independent flash memories. This approach is
Elmore Reba I.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Microcomputer including flash memory overwritable during... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microcomputer including flash memory overwritable during..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer including flash memory overwritable during... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3054963