Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-10-06
2002-06-18
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S036000
Reexamination Certificate
active
06408353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer, and more particularly, to the improvement of a sampling function of a retry requesting signal from peripheral units.
2. Description of the Related Art
In a prior art microcomputer including a central processing unit (CPU), at least one peripheral unit and a bus control unit connected therebetween, the bus control unit is constructed by a bus control circuit for controlling transfer of data, a strobe signal generating circuit for generating a strobe signal and transmitting the strobe signal to the peripheral unit, and a flip-flop for sampling a retry requesting signal from the peripheral unit in synchronization with a clock signal to generate a strobe requesting signal. The bus control circuit receives the strobe requesting signal to transfer data from the CPU to the peripheral unit. The strobe signal generating circuit receives the strobe requesting signal to generate another strobe signal. This will be explained later in datail.
In the above-described prior art microcomputer, however, if the peripheral unit is not synchronized with the clock signal while the CPU and the bus control unit are synchronized with the clock signal, unnecessary retry operations may be carried out and required retry operations may not be carried out. That is, the retry requesting signal may be sampled by the flip-flop to carry out a retry operation. On the other hand, in an abnormal state where the write operation fails, the sampling of the retry requesting signal by the flip-flop may be delayed which would delay the generation of an waiting signal for the CPU, so that a retry operation is not carried out.
SUMMARY OF THE INVENTION
It is an object of the present invention to be able to sample only required retry requesting signals in a microcomputer.
According to the present invention, in a microcomputer including a CPU, at least one peripheral unit and a bus control unit connected therebetween, the bus control unit is constructed by a bus control circuit for controlling transfer of data, a strobe signal generating circuit for generating a strobe signal and transmitting the strobe signal to the peripheral unit, a flip-flop for sampling a retry requesting signal from the peripheral unit in synchronization with the strobe signal to generate a strobe requesting signal, and a strobe requesting signal detecting circuit for detecting the strobe requesting signal to reset the flip-flop. The bus control circuit receives the strobe requesting signal to transfer data from the CPU to the peripheral unit. The strobe signal generating circuit receives the strobe requesting signal to generate another strobe signal.
If the active time period of the strobe signal is suitably adjusted, a retry requesting signal having a short period time in a normal state can not be sampled, while a retry requesting signal having a long period time in an abnormal state can be sampled.
REFERENCES:
patent: 5265243 (1993-11-01), Povenmire et al.
patent: 61-112272 (1986-05-01), None
patent: 62-156751 (1987-07-01), None
patent: 62-172456 (1987-07-01), None
patent: 63-66659 (1988-03-01), None
patent: 4-18657 (1992-01-01), None
Auve Glenn A.
Dickstein Shapiro Morin & Oshinsky LLP.
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