Computer graphics processing and selective visual display system – Computer graphics display memory system
Reexamination Certificate
2000-06-07
2003-08-26
Mancuso, Joseph (Department: 2697)
Computer graphics processing and selective visual display system
Computer graphics display memory system
C345S215000, C345S520000
Reexamination Certificate
active
06611270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer having an on-screen display in which a processing time required for a central processing unit is shortened to improve a software processing efficiency.
2. Description of Related Art
FIG. 11
is a block diagram showing the configuration of a conventional microcomputer having an on-screen display.
As shown in
FIG. 11
, a reference numeral
113
indicates a data storing unit including a read only memory (ROM) and a random access memory (RAM), and data used in the conventional microcomputer is stored in the data storing unit
113
. A reference numeral
114
indicates an on-screen display (OSD) RAM, and display data to be displayed on a cathode ray tube (CRT and not shown) is stored in the OSD-RAM
114
.
A reference numeral
111
indicates a central processing unit (CPU), and the conventional microcomputer is controlled by the CPU
111
. The accessing of the CPU
111
to the data storing unit
113
or the accessing of the CPU
111
to the OSD-RAM
114
is performed according to a data read/write request of the CPU
111
to perform a data reading or writing from/to the data storing unit
113
or to perform a display data writing to the OSD-RAM
114
. A reference numeral
115
indicates a 1-wait register, and an access mode value “0” indicating a no-wait access mode or an access mode value “1” indicating a 1-wait access mode is stored in the 1-wait register
115
according to an access mode instruction transmitted from the CPU
111
.
A reference numeral
112
indicates a bus interface unit (BIU). The BIU
112
controls the data read/write request transmitted from the CPU
111
to be transmitted to the data storing unit
113
or the OSD-RAM
114
. Also, the BIU
112
sets an access mode (for example, the no-wait access mode denoting a shortest access cycle or the 1-wait access mode denoting a double access cycle) of the conventional microcomputer according to the access mode value of the 1-wait register
115
to transmit the data read/write request of the CPU
111
to the data storing unit
113
or the OSD-RAM
114
and to make the CPU
111
access to the data storing unit
113
or the OSD-RAM
114
at the access mode.
A reference numeral
116
indicates an OSD logical circuit. An OSD-RAM read request signal S
2
of the OSD logical circuit
116
is transmitted to the OSD-RAM
114
to access to the OSD-RAM
114
at the access mode set by the BIU
112
to read out the display data stored in the OSD-RAM
114
.
A reference numeral
118
indicates a change-over switch, and a connection between the CPU
111
and the OSD-RAM
114
or a connection between the OSD logical circuit
116
and the OSD-RAM
114
is selected by the change-over switch
118
according to the data read/write request of the CPU
111
or the OSD-RAM read request signal S
2
of the OSD logical circuit
116
.
A reference numeral
117
indicates an address/data bus, and data read out or written from/in the data storing unit
113
, the data read/write request of the CPU
111
and the access mode value requested by the CPU
111
transmit through the address/data bus
117
.
An on-screen display of the conventional microcomputer is composed of the OSD-RAM
114
, the OSD logical circuit
116
and the change-over switch
118
.
In the above configuration, an operation of the conventional microcomputer is described.
FIG. 12
is a timing chart of signals used in the operation of the conventional microcomputer having the on-screen display.
When an access mode instruction is transmitted from the CPU
111
to the 1-wait register
115
through the BIU
112
, an access mode value “0” or an access mode value “1” is stored in the 1-wait register
115
under control of the BIU
112
, and an access mode of the conventional microcomputer is set by the BIU
112
according to a 1-wait signal Sw transmitted from the 1-wait register
115
. In cases where the access mode value “0” is set in the 1-wait register
115
, the BIU
112
sets a no-wait access mode denoting a shortest access cycle, so that an access of the CPU
111
to the ROM-RAM
113
or the OSD-RAM
114
is performed at the shortest access cycle. That is, no wait time is required of the CPU
111
. In contrast, in cases where the access mode value “1” is set in the 1-wait register
115
, the BIU
112
sets a 1-wait access mode denoting a double access cycle, so that an access of the CPU
111
to the ROM-RAM
113
or the OSD-RAM
114
is performed at the double access cycle which is two times of the shortest access cycle.
Thereafter, when a data read/write request is transmitted from the CPU
111
to the data storing unit
113
under control of the BIU
112
, the accessing of the CPU
111
to the data storing unit
113
is performed at the access mode set by the BIU
112
. Also, when a data read/write request is transmitted from the CPU
111
to the change-over switch
118
under control of the BIU
112
, the change-over switch
118
connects the CPU
111
with the OSD-RAM
114
, and the accessing of the CPU
111
to the OSD-RAM
114
is performed at the access mode set by the BIU
112
.
Also, when an OSD-RAM read request signal S
2
is transmitted from the OSD logical circuit
116
to the change-over switch
118
in synchronization with vertical and horizontal synchronization signals transmitted from the outside at a time that an CRT of the on-screen display is operated, the change-over switch
118
connects the OSD logical circuit
116
with the OSD-RAM
114
, the accessing of the OSD logical circuit
116
to the OSD-RAM
114
is performed at the access mode set by the BIU
112
, and the display data of the OSD-RAM
114
is read out to the OSD logical circuit
116
. Therefore, a display signal is produced in the OSD logical circuit
116
according to the display data, and the display signal is transmitted to the CRT in synchronization with the vertical and horizontal synchronization signals.
However, in cases where the OSD logical circuit
116
accesses to the OSD-RAM
114
when the CPU
111
accesses to the OSD-RAM
114
at the no-wait access mode, because the CPU
111
and the OSD logical circuit
116
cannot simultaneously access to the OSD-RAM
114
, there is a problem that a wrong operation is performed in the conventional microcomputer.
To avoid this problem in the conventional microcomputer, the access mode value “1” indicating the 1-wait access mode is set in the 1-wait register
115
during the operation of the on-screen display, and the CPU
111
and the OSD logical circuit
116
access to the OSD-RAM
114
in time-division at the double access cycle. For example, as shown in
FIG. 12
, when the operation of the on-screen display is started at a time T
100
, the access mode value “1” is set in the 1-wait register
115
to transmit a 1-wait signal Sw of a high level to the BIU
112
, and the conventional microcomputer is set to the 1-wait access mode. Thereafter, in cases where the accessing of the CPU
111
to the OSD-RAM
114
and the accessing of the OSD logical circuit
116
to the OSD-RAM
114
are simultaneously performed in a time-period T
100
of one double access cycle by transmitting a CPU access address of the data read/write request indicating the OSD-RAM
114
and an OSD-RAM read request signal S
2
of the OSD logical circuit
116
to the change-over switch
118
, the CPU
111
accesses to the OSD-RAM
114
during a first half time-period T
121
of the time-period T
100
, and the OSD logical circuit
116
accesses to the OSD-RAM
114
during a second half time-period T
122
of the time-period T
100
.
However, because the conventional microcomputer is set to the 1-wait access mode during the operation of the on-screen display, a time-period of each access of the CPU
111
to the data storing unit
113
or the OSD-RAM
114
is doubled to two clocks of a system clock signal during the operation of the on-screen display as compared with that at the no-wait access mode. For example, when the CPU
111
accesses to the data storing unit
113
during the operation of t
Burns Doane , Swecker, Mathis LLP
Caschera Antonio
Mancuso Joseph
Mitsubishi Denki & Kabushiki Kaisha
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