Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1998-11-18
2001-09-04
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C341S144000, C341S155000
Reexamination Certificate
active
06286065
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer and in particular, to a microcomputer having a built-in A/D converter circuit.
2. Description of the Related Art
FIG. 5
is a block diagram showing a configuration of such a microcomputer of a conventional type. As shown in
FIG. 5
, this conventional microcomputer includes: a data processor circuit block
2
; an A/D converter circuit block
3
; an I/O circuit
1
having a P channel MOS transistor
8
, an N channel MOS transistor
9
, and a NAND circuit
10
; and an external terminal
11
. A wiring connecting the external terminal
11
to the I/O circuit
1
and to the A/D converter circuit block
3
has wire resistances, i.e., parasitic resistances explicitly depicted as
4
,
5
, and
7
. It should be noted that this is an example of a microcomputer that has reduced the number of terminals by sharing a single terminal as the external terminal used during a normal operation of the microcomputer and as an input terminal of the A/D converter circuit block during an A/D conversion operation.
In
FIG. 5
, when the microcomputer executes a normal processing operation in response to a data signal from the external terminal
11
, the data processor circuit block
2
outputs control signals
101
and
102
either at “H” or “L” level for supply to corresponding gates of the P channel MOS transistor
8
and the N channel MOS transistor
9
, respectively. Moreover, the data processor circuit block
2
outputs an input control signal
103
which is supplied when at “L” level to the NAND circuit
10
. In this state, a data signal from the external terminal
11
is supplied to the NAND circuit
10
while affected by the ON/OFF operation state of the P channel MOS transistor
8
and the N channel MOS transistor
9
. In the NAND circuit
10
, the data signal is AND-ed with the input control signal
103
at “L” level and a resultant signal is supplied as an LSI input signal
104
to the data processor circuit block
2
, where a predetermined processing is executed corresponding to the data signal supplied from the external terminal
11
.
Moreover, when the microcomputer executes an A/D conversion, the data processor circuit block
2
outputs a control signal
101
at “H” level and a control signal
102
at “L” level. Upon reception of these control signals
101
and
102
, the P channel MOS transistor
8
and the N channel MOS transistor
9
both enter the OFF state. Moreover, the data processor circuit block
2
outputs the input control signal
103
at “H” level for supply to the NAND circuit
104
. In this state, a data signal from the external terminal
11
to be subjected to an A/D conversion is cut off by a circuit formed by the P channel MOS transistor
8
and the N channel MOS transistor
9
, whereas an input impedance of the NAND circuit
10
is in an open state. Accordingly, the data signal from the external terminal
11
to be subjected to the A/D conversion passes through the parasitic resistances
4
and
7
to reach the A/D converter circuit block
3
so as to be subjected to a predetermined A/D conversion. Here, as has been described above, the input control signal
103
from the data processor circuit block
2
is supplied as “H” level to the NAND circuit
104
. Accordingly, the data signal supplied via the parasitic resistances
4
and
5
is AND-ed in the NAND circuit
10
, which outputs an LSI input signal
104
always at “L” level when supplied to the data processor circuit block
2
. It should be noted that during this A/D conversion, if no off-leak current is generated in the I/O circuit
1
, no leak current is generated at the input side of the A/D converter circuit block
3
which is connected to a capacitor via an A/D conversion switching transfer gate (not depicted). Consequently, no leak current is generated at the input side of the A/D converter circuit block, and regardless of values of the parasitic resistances
4
and
7
, a potential of a data signal at the node B in
FIG. 5
is at a level identical to the input potential to the external terminal
11
. Thus, regardless of presence or absence of parasitic resistances, a data signal is applied to the A/D converter circuit block
3
without any level loss.
In the aforementioned conventional microcomputer sharing the single external terminal with an input terminal of the A/D converter circuit block, with increase in the integration of the semiconductor integrated circuit constituting the microcomputer, it has become impossible to arrange the I/O circuit at a sufficient distance from various noise sources. Accordingly, a noise generated from such a noise source causes a level fluctuation of the gates of the P channel MOS transistor
8
and the N channel MOS transistor
9
, which in turn generates an off-leak current in the I/O circuit
1
. Because of the parasitic resistance
4
, the off-leak current causes a level fluctuation of a data signal inputted to the A/D converter circuit block from the external terminal. Suppose Vi is a voltage level of a data signal supplied to the external terminal
11
; r
4
and r
5
are values of the parasitic resistances
4
and
5
; and &agr; is a voltage fluctuation value at the node A caused by an off-leak current of the I/O circuit
1
. For the voltage level V
i
of the data signal supplied to the external terminal
11
, the data signal at the node B of the input terminal of the A/D converter circuit block
3
has a potential level V
B
that can be expressed as follows.
V
B
=V
i
+&agr;[r
4
/(
r
4
+
r
5
)] (1)
Accordingly, the potential level V
B
of the data signal supplied to the A/D converter circuit block
3
, as shown above in the Equation (1), fluctuates according to the voltage fluctuation caused by the off-leak current in the I/O circuit
1
and the resistance value of the parasitic resistances
4
and
5
. This significantly deteriorates the A/D conversion accuracy.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a microcomputer having a built-in A/D converter circuit and sharing an external terminal with an input terminal of the A/D converter so as to reduce the number of necessary terminals, enabling to reduce the size and weight of the semiconductor integrated circuit while eliminating deterioration of the A/D converter circuit due to the reduction in the number of the terminals.
The microcomputer according to the present invention comprises: an internal circuit having a data processing function; a built-in A/D converter circuit connected to the internal circuit; an I/O circuit connected to the internal circuit; an external terminal for input/output shared by an input terminal of the A/D converter circuit;
a first branch wire connecting the external terminal via the I/O circuit to the internal circuit; a second branch wire connecting the external terminal to the A/D converter circuit, and a resistor inserted on the first branch wire connecting the external terminal to the I/O circuit and having a sufficiently higher resistance than a parasitic resistance of the first branch wire.
It should be noted that a main wire may be provided between the external terminal and a branching point of the first branch wire and the second branch wire.
The I/O circuit may include: a first-conductive field effect transistor (FET) having a source connected to a high-potential power source, a gate supplied with a first control signal from the internal circuit, and a drain connected to a terminal of the predetermined resistor; a second-conductive field effect transistor (FET) having a drain connected to the drain of the first-conductive FET, a gate supplied with a second control signal form the internal circuit, and a source connected to a low-potential power source; and a NAND circuit having a first input terminal connected to the terminal of the predetermined resistor, a second input terminal supplied with an input control signal from the internal circuit, and an output terminal connected to the internal c
Foley & Lardner
NEC Corporation
Shin Christopher B.
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