Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2000-06-21
2004-02-24
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S243000
Reexamination Certificate
active
06697938
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a microcomputer which executes various instructions of a program stored in its built-in memory or in an external memory.
For example, a microcomputer executes a real arithmetic operation (i.e, a calculation using real numbers). In this case, one method is to incorporate an auxiliary arithmetic unit to the microcomputer, wherein the auxiliary arithmetic unit is dedicated to the real arithmetic processing. Another method is to perform software calculations based on a plurality of CPU instructions. The former method is not preferable in that the chip size becomes large and the cost increases due to addition of the hardware dedicated to the real arithmetic processing. Accordingly, the latter method is generally preferable.
In view of the above, a conventional microcomputer runs a real arithmetic processing program as a subroutine, so that the microcomputer when executing a main routine or the like can jump to this subroutine (in other words, so that the microcomputer can invoke the real arithmetic subroutine) to execute the real processing.
However, a recently used RISC computer, i.e., a reduced (or restricted) instruction set computer, implements a branch or a jump to the subroutine in accordance with a plurality of instructions or in accordance with a long instruction whose length is longer than a minimum instruction length. The minimum instruction is shortest in bit length. For example, the long instruction is not less than 4 bytes when the minimum instruction is 2 bytes.
In general, a branch instruction, used for jumping to a subroutine, is set to be able to jump to an arbitrary address in an entire memory space. To this end, the bit length of an address portion in this branch instruction tends to be long. The address portion in a branch instruction is called “operand” which is a data portion representing the branch address. This is why a plurality of instructions or a long instruction is required in executing a branch instruction in the above-described RISC computer. The memory space is an address space accessibly by the microcomputer.
Accordingly, conventional microcomputers had to handle an increased number of programs. As a result, there was a tendency that their built-in memories cannot store all of the necessary programs.
Increase of the overall program size may be absorbed by an external memory provided outside the microcomputer. However, rapid speed-up of computations required in recent microcomputers tends to negate the use of such external memories because the external memories are slow in their response speeds compared with those of the built-in memories. In other words, accessing the external memories inevitably results in a relatively long time required for outputting an address to an address bus and for accomplishing reading of data. Thus, when the programs are stored in an external memory, a long time is necessary to accomplish the processing for invoking or calling the real arithmetic subroutine. In other words, the ability to execute the real arithmetic subroutine is decreased.
As described above, an ordinary branch instruction has a length longer than the minimum instruction length. Thus, completely reading the branch instruction requires a plurality of accesses to the memory. As described above, the external memories are slow in their response speeds. Therefore, in accordance with the number of accesses to the external memory, the processing time becomes more longer in accomplishing the reading and execution of the branch instruction. The start timing for the real arithmetic subroutine is delayed.
The above explanation is based on an example of the real arithmetic processing. Like the real arithmetic processing, the integer division processing and the bit data processing are executed in accordance with a software rather than using a dedicated hardware. Hence, the above-described problems will arise similarly in the integer division processing and in the bit data processing. The integer division processing is the arithmetic processing for dividing an integer by another integer. The bit data processing is the bit arithmetic processing using bit data.
SUMMARY OF THE INVENTION
In view of the above, the present invention has an object to provide a microcomputer capable of running a subroutine for executing at least one of the real arithmetic processing, the integer division processing and the bit data processing, wherein a required program size can be reduced and, when the programs are stored in an external memory, real time executability of each processing can be improved.
To accomplish the above and other related objects, the present invention provides a microcomputer including a built-in memory and having access to an external memory via a bus. The program to be executed in the microcomputer is stored in the built-in memory or in the external memory.
More specifically, the microcomputer of the present invention executes a specific area branch instruction as an executable instruction. The specific area branch instruction is a special branch instruction which is restricted to jump to only a specific area of a memory space and is a single instruction having a minimum instruction length.
Furthermore, the microcomputer of the present invention allocates a selected subroutine to the specific area of the memory. The selected subroutine is one of a real arithmetic subroutine for executing the real arithmetic processing, an integer division subroutine for executing the integer division processing, and a bit handling subroutine for executing the bit data processing. And, a program of the microcomputer is configured to jump to the selected subroutine (i.e., any one of the real arithmetic subroutine, the integer division subroutine, and the bit handling subroutine) allocated to the specific area in response to the specific area branch instruction.
As described above, the microcomputer of the present invention substantially restricts the jump area of the specific area branch instruction to the specific area in the entire memory space. The specific area branch instruction is a single instruction having the minimum instruction length. The subroutine, allocated to the specific area of the memory, is selected from the group consisting of the real arithmetic subroutine, the integer division subroutine, and the bit handling subroutine. The subroutine allocated to the specific area is invoked in response to the specific area branch instruction.
Accordingly, the microcomputer of the present invention can reduce the required program size to a level corresponding to the minimum instruction length, in invoking any one of the real arithmetic subroutine, the integer division subroutine, and the bit handling subroutine (or in branching to any one of these subroutines). As a result, the microcomputer can reduce the overall program size, thereby enabling its built-in memory to store all of the necessary programs. Alternatively, the present invention makes it possible to use a built-in memory having a smaller storage capacity.
As the specific area branch instruction has the minimum instruction length, only one access to the memory is required to read this instruction. In other words, the reading of the specific area branch instruction is accomplished within a single instruction reading cycle. When the programs are stored in an external memory, the microcomputer of the present invention can invoke any one of the real arithmetic subroutine, the integer division subroutine, and the bit handling subroutine with a minimum increase of the execution time. In other words, in starting each subroutine, the microcomputer of the present invention can suppress a delay time to a minimum level. And, the microcomputer of the present invention can improve the real time executability in each of the real arithmetic processing, the integer division processing, and the bit arithmetic processing.
REFERENCES:
patent: 3366929 (1968-01-01), Mullery et al.
patent: 4285036 (1981-08-01), Kitagawa et al.
patent: 4363091 (1982-12-01), Pohlman et al.
patent
Ishihara Hideaki
Kamiya Masahiro
Denso Corporation
Posz & Bethards, PLC
Tsai Henry W. H.
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