Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-08-29
2006-08-29
Beausoliel, Robert (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S031000
Reexamination Certificate
active
07100086
ABSTRACT:
An object is to provide a microcomputer, electronic instrument and debugging system which can realize an on-chip debugging function through a reduced size of instruction code or a reduced circuit scale. A main monitor section (16) converts a debugging command into a primitive command. A mini monitor section (14) transfers data to and from the main monitor section (16) to execute a primitive command determined based on the receive data. The primitive commands include go, write and read commands. A control register having its address allocated on a memory map in the debugging mode is provided together with a mini monitor RAM. The mini monitor section (14) serving as a slave is connected to the main monitor section (16) serving as a master through a half-duplex bidirectional communication line so that transfer data can be fixed-length. The receive data includes a command identifying data. A mini monitor program has been stored in a ROM. The mini monitor section (14) and main monitor section (16) use a clock in common to generate a sampling clock while transferring data in the start-stop synchronization.
REFERENCES:
patent: 5771240 (1998-06-01), Tobin et al.
patent: 6145123 (2000-11-01), Torrey et al.
patent: 6154856 (2000-11-01), Madduri et al.
patent: 6185522 (2001-02-01), Bakker
patent: 6279123 (2001-08-01), Mulrooney
patent: 6314530 (2001-11-01), Mann
patent: 6484273 (2002-11-01), Chang
patent: 6502210 (2002-12-01), Edwards
patent: 60-72034 (1985-04-01), None
patent: 63-303437 (1988-12-01), None
patent: 64-3745 (1989-01-01), None
patent: 1-286030 (1989-11-01), None
patent: 01-287752 (1989-11-01), None
patent: 02-264339 (1990-10-01), None
patent: 06-103104 (1994-04-01), None
patent: 8-221297 (1996-08-01), None
IEEE Standard Test ACCESS Port and Boundry Scan Architecture, IEEE, 1993 IEEE Std 1149.1-1990.
Isao Yoshida, “Function and Application of Ser. Port”, Transistor Gijutsu, vol. 32, No. 10, Oct. 1, 1995, pp. 204-247 (w/partial English language translation of article).
Hijikata Yoichi
Kudo Makoto
Beausoliel Robert
Bonzo Bryce P.
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